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CONTROL DATA
6400/6500/6600 COMPUTER SYSTEMS
Reference Manual

INDEX TO CENTRAL PROCESSOR INSTRUCTIONS

NUMERICAL

OCTAL CODE MNEMONIC ADDRESS NAME
00 PS . Program stop 3-23
010 RJ K Return jump to K 3-43
011 REC Bj + K Read Extended Core Storage 3-46
012 WEC Bj + K Write Extended Core Storage 3-47
02* JP Bi + K Jump to Bi + K 3-44
030** ZR Xj K Jump to K if Xj = 0 3-44
031** NZ Xj K Jump to K if Xj != 0 3-44
032** PL Xj K Jump to K if Xj is plus (positive)3-44
033** NG Xj K Jump to K if Xj is negative 3-44
034** IR Xj K Jump to K if Xj is in range 3-44
035** OR Xj K Jump to K if Xj is out of range 3-44
036** DF Xj K Jump to K if Xj is definite 3-44
037** ID Xj K Jump to K if Xj is indefinite 3-44
04* EQ Bi Bj K Jump to K if Bi = Bj 3-45
05* NE Bi Bj K Jump to K if Bi != Bj 3-45
06* GE Bi Bj K Jump to K if Bi >= Bj 3-45
07* LT Bi Bj K Jump to K if Bi < Bj 3-45
10 BXi Xj Transmit Xj to Xi 3-29
11 BXi Xj * Xk Logical product of Xj and Xk to Xi 3-29
12 BXi Xj + Xk Logical sum of Xj and Xk to Xi 3-30
13 BXi Xj - Xk Logical difference of Xj and Xk to Xi 3-30
14 BXi -Xk Transmit the comp. of Xk to Xi 3-30
15 BXi -Xk * XjLogical product of Xj and Xk comp. to Xi3-31
16 BXi -Xk + XjLogical sum of Xj and Xk comp. to Xi 3-31
17 BXi -Xk - XjLogical difference of Xj and Xk comp. to Xi3-32
20 LXi jk Left shift Xi, jk places 3-32
21 AXi jk Arithmetic right shift Xi, jk places 3-32
22 LXi Bj Xk Left shift Xk nominally Bj places to Xi3-33
23 AXiBj XkArithmetic right shift Xk nominally Bj places to Xi 3-33
24 NXi Bj Xk Normalize Xk in Xi and Bj 3-34
25 ZXi Bj Xk Round and normalize Xk in Xi and Bj 3-34
26 UXi Bj Xk Unpack Xk to Xi and Bj 3-35
27 PXi Bj Xk Pack Xi from Xk and Bj 3-36
30 FXi Xj + Xk Floating sum of Xj and Xk to Xi 3-37
31 FXi Xj - Xk Floating difference of Xj and Xk to Xi 3-37
32 DXi Xj + Xk Floating DP sum of Xj and Xk to Xi 3-38
33 DXi Xj - Xk Floating DP difference of Xj and Xk to Xi 3-38
34 RXi Xj + Xk Round floating sum of Xj and Xk to Xi 3-38
35 RXi Xj - Xk Round floating difference of Xj and Xk to Xi3-39
36 IXi Xj + Xk Integer sum of Xj and Xk to Xi 3-28
37 IXi Xj - Xk Integer difference of Xj and Xk to Xi 3-28
40 FXi Xj * Xk Floating product of Xj and Xk to Xi 3-40
41 RXi Xj * Xk Round floating product of Xj and Xk to Xi 3-40
42 DXi Xj * Xk Floating DP product of Xj and Xk to Xi 3-41
43 MXi jk Form mask in Xi, jk bits 3-36
44 FXi Xj / Xk Floating divide Xj by Xk to Xi 3-41
45 RXi Xj / Xk Round floating divide of Xj by Xk to Xi 3-42
46 NO . No operation (Pass) 3-23
47 CXi Xk Count the number of 1's in Xk to Xi 3-28
50 SAi Aj + K Set Ai to Aj + K 3-24
51 SAi Bj + K Set Ai to Bj + K 3-24
52 SAi Xj + K Set Ai to Xj + K 3-24
53 SAi Xj + Bk Set Ai to Xj + Bk 3-24
54 SAi Aj + Bk Set Ai to Aj + Bk 3-24
55 SAi Aj - Bk Set Ai to Aj - Bk 3-24
56 SAi Bj + Bk Set Ai to Bj + Bk 3-24
57 SAi Bj - Bk Set Ai to Bj - Bk 3-24
60 SBi Aj + K Set Bi to Aj + K 3-26
61 SBi Bj + K Set Bi to Bj + K 3-26
62 SBi Xj + K Set Bi to Xj + K 3-26
63 SBi Xj + Bk Set Bi to Xj + Bk 3-26
64 SBi Aj + Bk Set Bi to Aj + Bk 3-26
65 SBi Aj - Bk Set Bi to Aj - Bk 3-26
66 SBi Bj + Bk Set Bi to Bj + Bk 3-26
67 SBi Bj - Bk Set Bi to Bj - Bk 3-26
70 SXi Aj + K Set Xi to Aj + K 3-26
71 SXi Bj + K Set Xi to Bj + K 3-26
72 SXi Xj + K Set Xi to Xj + K 3-26
73 SXi Xj + Bk Set Xi to Xj + Bk 3-27
74 SXi Aj + Bk Set Xi to Aj + Bk 3-27
75 SXi Aj - Bk Set Xi to Aj - Bk 3-27
76 SXi Bj + Bk Set Xi to Bj + Bk 3-27
77 SXi Bj - Bk Set Xi to Bj - Bk 3-27

ALPHABETICAL

MNEMONIC OCTAL CODE ADDRESS NAME PAGE
AXi 21 jk Arithmetic right shift Xi, jk places 3-32
AXi 23 Bj XkArithmetic right shift Xk nominally Bj places to Xi3-33
BXi 10 Xj Transmit Xj to Xi 3-29
BXi 11 Xj * Xk Logical product of Xj and Xk to Xi 3-29
BXi 12 Xj + Xk Logical sum of Xj and Xk to Xi 3-30
BXi 13 Xj - Xk Logical difference of Xj and Xk to Xi 3-30
BXi 14 -Xk Transmit the comp. of Xk to Xi 3-30
BXi 15 -Xk * XjLogical product of Xj and Xk comp. to Xi 3-31
BXi 16 -Xk + XjLogical sum of Xj and Xk comp. to Xi 3-31
BXi 17 -Xk - XjLogical difference of Xj and Xk comp. to Xi 3-32
CXi 47 Xk Count the number of 1's in Xk to Xi 3-28
DF**036 Xj K Jump to K if Xj is definite 3-44
DXi 32 Xj + Xk Floating DP sum of Xj and Xk to Xi 3-38
DXi 33 Xj - Xk Floating DP difference of Xj and Xk to Xi 3-38
DXi 42 Xj * Xk Floating DP product of Xj and Xk to Xi 3-41
EQ* 04 Bi Bj K Jump to K if Bi = Bj 3-45
FXi 30 Xj + Xk Floating sum of Xj and Xk to Xi 3-37
FXi 31 Xj - Xk Floating difference of Xj and Xk to Xi 3-37
FXi 40 Xj * Xk Floating product of Xj and Xk to Xi 3-40
FXi 44 Xj / Xk Floating divide Xj by Xk to Xi 3-41
GE* 06 Bi Bj K Jump to K if Bi >= Bj 3-45
ID**037 Xj K Jump to K if Xj is indefinite 3-44
IR**034 Xj K Jump to K if Xj is in range 3-44
IXi 36 Xj + Xk Integer sum of Xj and Xk to Xi 3-28
IXi 37 Xj - Xk Integer difference of Xj and Xk to Xi 3-28
JP* 02 Bi + K Jump to Bi + K 3-44
LT* 07 Bi Bj K Jump to K if Bi < Bj 3-45
LXi 20 jk Left shift Xi, jk places 3-32
LXi 22 Bj Xk Left shift Xk nominally Bj places to Xi 3-33
MXi 43 jk Form mask in Xi, jk bits 3-36
NE* 05 Bi Bj K Jump to K if Bi != Bj 3-45
NG**033 Xj K Jump to K if Xj is negative 3-44
NO 46 . No operation (Pass) 3-23
NXi 24 Bj Xk Normalize Xk in Xi and Bj 3-34
NZ**031 Xj K Jump to K if Xj != 0 3-44
OR**035 Xj K Jump to K if Xj is out of range 3-44
PL**032 Xj K Jump to K if Xj is plus (positive) 3-44
PS 00 . Program stop 3-23
PXi 27 Bj Xk Pack Xi from Xk and Bj 3-36
REC 011 Bj + K Read Extended Core Storage 3-46
RJ 010 K Return jump to K 3-43
RXi 34 Xj + Xk Round floating sum of Xj and Xk to Xi 3-38
RXi 35 Xj - Xk Round floating difference of Xj and Xk to Xi3-39
RXi 41 Xj * Xk Round floating product of Xj and Xk to Xi 3-40
RXi 45 Xj / Xk Round floating divide of Xj by Xk to Xi 3-42
SAi 50 Aj + K Set Ai to Aj + K 3-24
SAi 51 Bj + K Set Ai to Bj + K 3-24
SAi 52 Xj + K Set Ai to Xj + K 3-24
SAi 53 Xj + Bk Set Ai to Xj + Bk 3-24
SAi 54 Aj + Bk Set Ai to Aj + Bk 3-24
SAi 55 Aj - Bk Set Ai to Aj - Bk 3-24
SAi 56 Bj + Bk Set Ai to Bj + Bk 3-24
SAi 57 Bj - Bk Set Ai to Bj - Bk 3-24
SBi 60 Aj + K Set Bi to Aj + K 3-26
SBi 61 Bj + K Set Bi to Bj + K 3-26
SBi 62 Xj + K Set Bi to Xj + K 3-26
SBi 63 Xj + Bk Set Bi to Xj + Bk 3-26
SBi 64 Aj + Bk Set Bi to Aj + Bk 3-26
SBi 65 Aj - Bk Set Bi to Aj - Bk 3-26
SBi 66 Bj + Bk Set Bi to Bj + Bk 3-26
SBi 67 Bj - Bk Set Bi to Bj - Bk 3-26
SXi 70 Aj + K Set Xi to Aj + K 3-26
SXi 71 Bj + K Set Xi to Bj + K 3-26
SXi 72 Xj + K Set Xi to Xj + K 3-26
SXi 73 Xj + Bk Set Xi to Xj + Bk 3-27
SXi 74 Aj + Bk Set Xi to Aj + Bk 3-27
SXi 75 Aj - Bk Set Xi to Aj - Bk 3-27
SXi 76 Bj + Bk Set Xi to Bj + Bk 3-27
SXi 77 Bj - Bk Set Xi to Bj - Bk 3-27
UXi 26 Bj Xk Unpack Xk to Xi and Bj 3-35
WEC 012 Bj + K Write Extended Core Storage 3-47
ZR** 030 Xj K Jump to K if Xj = 0 3-44
ZXi 25 Bj Xk Round and normalize Xk in Xi and Bj 3-34
*Jump to K + Bi and Jump to K if Bi---tests made in Increment unit.
**Jump to K if Xj---tests made in Long Add unit.
Rev. A


RECORD of REVISIONS
REVISION NOTES
A
(4-5-66)
This manual obsoletes the 6600 Computer System Reference Manual, Pub. No. 60045000. Publication Change Order CA13186. Addition and deletion of information for technical accuracy.
Title changed to 6400/6600 Computer Systems Reference Manual. This edition obsoletes all previous editions.
B
(9-1-66)
Publication Change Order 14568. Pages 3-13 B-4, B-9 B-12, B-13, B-14 B-15 B-16, D-5, 9-1-66 and Index-2 revised.
C
(10-27-66)
Publication Change a Order 15036. Page D-6 revised.
D
(2-21-67)
Publication Change Order 15866. Addition of 6500 information; title changed to 6400/6500/6600 Computer Systems Reference Manual. The following pages revised: cover and title page, iv, v, frontispiece, 1-1, 1-2, 1-3, 1-4, 1-5, 1-7, 1-8, 3-1, 3-2, 3-6, 3-7, 3-12, 3-16, 3-20, 3-51, 4-1, 4-13, 4-24, 4-25, 4-29, 4-30, 4-36, 5-1, 6-1, 6-4, Appendix A title page, A-1, A-2, A-3, A-4, A-5, A-6, B-2, B-3, B-5, B-6, B-7, B-8, C-1, D-1, D-2, D-3, D-4, D-6, and Comment Sheet.
E
(5-16-67)
Field Change Order 15829. Changes included in Publications Change Order 19635.
F
(5-16-67)
Publications Change Order 19635. Deletion of ECS information, addition of COMPASS mnemonics, miscellaneous additions and corrections. The following pages revised: Title Page and Record of Revisions, iii, iv, v, 1-3, 1-8, 3-9, 3-11, 3-23, 3-46, 3-47, 4-7, 4-10, 4-25, 4-26, 4-29, 4-30, 4-31, 4-37, 4-38, 4-39, 6-2, 6-4, A-3, A-4, B-6, Appendix D Title Page, D-1 through D-6, Index-1, and Index-2.
G
(9-26-68)
Manual revised; includes Engineering Change Order 20617, publication change only. Pages 3-8, 3-13, and 4-8 revised.
H
(2-21-69)
Manual revised; includes Engineering Change Order 21720, publication change only. Pages iii, v, 3-3, 3-4, 3-5, 3-6, 3-7, 3-34, 3-35, 3-42, 3-43, D-2, D-4 and D-5 revised.
FORM CA230 REV. 1-67

Pub. No. 60100000
 1965, 1966, 1967, 1968, 1969
by Control Data Corporation

Printed in United States of America

.
Address comments concerning this
manual to:
    Control Data Corporation
    Technical Publications Department
    4201 North Lexington Avenue
    St. Paul, Minnesota 55112

or use Comment Sheet in the back of
this manual.

CONTENTS

1. System Description
Introduction 1-1
Systems Characteristics Summary 1-3
System Characteristics
1-4
Central Processor Characteristics
1-4
Peripheral and Control Processor Characteristics
1-5
Central Memory Characteristics
1-6
Display Console Characteristics
1-7
Systems Options 1-8
.
2. Central Memory
Organization 2-1
Address Format 2-1
Central Memory Access 2-1
Memory Protection 2-2
.
3. Central Processor
Organization 3-1
Central Processor Programming 3-4
Functional Units
3-5
Instruction Formats
3-5
Operating Registers
3-6
Exchange Jump
3-9
Exit Mode
3-11
Floating Point Arithmetic
3-15
Fixed Point Arithmetic
3-21
Description of Central Processor Instructions
3-22
Program Stop and No Operation
3-23
Increment
3-24
Fixed Point Arithmetic
3-28
Logical
3-29
Shift
3-32
Floating Point Arithmetic
3-37
Branch
3-43
Extended Core Storage Communication
3-46
.
4. Peripheral and Control Processors
Organization 4-1
Peripheral Processor Programming 4-6
Instruction Formats
4-6
Address Modes
4-6
Registers
4-8
Description of Peripheral Processor Instructions
4-9
No Operation
4-10
Data Transmission
4-11
Arithmetic
4-13
Shift
4-16
Logical
4-16
Replace
4-19
Branch
4-22
Central Processor and Central Memory
4-24
Input / Output
4-27
Access to Central Memory
4-32
Input and Output
4-35
Real- Time Clock
4-39
.
5. System Interrupt
Introduction 5-1
Hardware Provisions for Interrupt 5-1
Exchange Jump
5-1
Channel and Equipment Status
5-1
Exit Mode
5-2
.
6. Manual Control
Introduction 6-1
Dead Start 6-1
Load Mode
6-1
Sweep Mode
6-2
Dump Mode
6-2
Console 6- 4
Keyboard Input
6-4
Display
6-4

Appendix A Augmented I/O Buffer and Control (6416)
Appendix B Instruction Execution Times
Appendix C Non-Standard Floating Point Arithmetic
Appendix D Compass Mnemonics

FIGURES

1-1 CONTROL DATA 6400/6500 6600 Computer Systems 1-1
1-2 Concurrent Operations in the 6400/6500/6600 1-2
1-3 Block Diagram of 6600 System 1-6
1-4 Block Diagram of 6400 and 6500 Systems 1-7
2-1 Memory Map 2-3
3-1 Central Processor Instruction Formats 3-6
3-2 Central Processor Operating Registers 3-7
3-3 Exchange Jump Package 3-9
3-4 Detecting and Handling Central Processor Stops 3-14
4-1 Flow Chart: 6400/6500/6600 Systems 4-1
4-2 Peripheral and Control Processors 4-5
6-1 Dead Start Panel 6-3
6-2 Display Console 6-5
6-3 Sample Display 6-6

TABLES

3-1 Central Processor Differences 3-1
3-2 Functional Units 3-5
3-3 Exit Mode: Address Out of Bounds 3-13
3-4 Range of Permissible Exponents 3-16
3-5 Indefinite Forms 3-17
3-6 Overflow and Underflow Conditions 3-20
3-7 Central Processor Instruction Designators 3-22
4-1 Addressing Modes for Peripheral and Control Processor Instructions 4-8
4-2 Peripheral and Control Processor Instruction Designators 4-10

A CONTROL DATA 6000 SERIES COMPUTER SYSTEM

Display console (foreground) - includes a keyboard for manual input and operator control and two 10-inch display tubes for display of problem status and operator directives.

Mainframe (center) - contains 10 Peripheral and Control Processors, Central Processor, Central Memory, some I/O synchronizers. The main frame in this photo is that of the 6600 Computer System; the mainframes for the 6400 and 6500 systems differ in physical appearance, depending on options included in the systems.

CONTROL DATA 607 Magnetic Tape Transport (left front) - 1 / 2-inch magnetic tape units for supplementary storage; binary or BCD data handled at 200, 556, or 800 bpi.

CONTROL DATA 626 Magnetic Tape Transport (left rear) - 1-inch magnetic tape units for supplementary storage; binary data handled at 800 bpi.

CONTROL DATA 405 Card Reader (right front) - reads binary or BCD cards at 1200 card per minute rate.

Disk file (right rear) - supplementary mass storage device; holds 500 million bits of information.

1. SYSTEM DESCRIPTION

INTRODUCTION

The CONTROL DATA* 6400, 6500, and 6600 Computer Systems are three large-scale, solid-state, general-purpose digital computing systems. The advanced design techniques incorporated in these systems provide for extremely fast solutions to data processing, scientific, and control center problems, as well as multiprocessing, time-sharing, and management information applications.

Each of the computing systems has at least eleven independent computers (Figure 1-1). Ten of these, constructed with the peripheral and operating system in mind, are Peripheral and Control Processors. Each of these ten has separate memory and can execute programs independently of each other or the Central Processor.

Figure 1-1. CONTROL DATA 6400/6500/6600 Computer Systems

The eleventh computer, the Central Processor, is a very high speed arithmetic device. The common element of the Peripheral and Control Processors and the Central Processor is a large Central Memory.

In solving a problem, one or more Peripheral and Control Processors are used for high speed information transfer in and out of the system and to provide operator control. A number of problems may operate concurrently by time-sharing the Central Processor. (To facilitate this, the Central Processor may operate in Central Memory only within address bounds prescribed by a Peripheral and Control Processor.) Further concurrency is obtained within the Central Processor by parallel action of various functional segments. Similarly, Central Memory is organized in 32 logically independent banks of 4096 words (60-bit). Several banks may be in operation simultaneously, thereby minimizing execution time. The multiple operating modes of all segments of the computer, in combination with high-speed transistor circuits, produce a very high over-all computing speed.

Figure 1-2.Concurrent Operations in the 6400/6500/6600

The Peripheral and Control Processor input/output facility provides a flexible arrangement for very high speed communication with a variety of I/O devices. Some of the I/O devices available with the 6400, 6500, and 6600 systems are listed below. (Refer to the 6000 Series Peripheral Reference Manual for additional external equipment information. )

SYSTEMS CHARACTERISTICS SUMMARY

The following summary lists characteristics of the 6400, 6500, and 6600 Computer Systems. Where characteristics differ between the systems, differences are noted; otherwise, characteristics listed are common to all systems.

System Characteristics

Central Processor Characteristics

6600

6400 and 6500

Common Central Processor Characteristics

Peripheral and Control Processor Characteristics

Central Memory Characteristics

Display Console Characteristics



Figure 1-4.Block Diagram of 6400 and 6500 Systems

SYSTEMS OPTIONS

The foregoing summary of characteristics assumed a 6400, 6500, or 6600 system with 10 Peripheral and Control Processors, a Central Processor (except for the 6500 system with its two identical Central Processors), and Central Memory with 131, 072 words (60-bit) of magnetic core storage.

Options listed below are available within each system unless otherwise noted.

2. CENTRAL MEMORY

ORGANIZATION

Central Memory is organized into 32K, 65K, or 131K words (60-bit) in 8, 16, or 32 banks of 4096 words each. The banks are logically independent, and consecutive addresses go to different banks. Banks may be phased into operation at minor cycle intervals, resulting in very high Central Memory operating speed. The Central Memory address and data control mechanisms permit a word to move to or from Central Memory every minor cycle.

ADDRESS FORMAT

The location of each word in Central Memory is identified by an assigned number (address), which consists of 18 bits. Address formats are shown below for 8-bank(32K), 16-bank (65K), and 32-bank (131K) systems. Within the address format, the bank portion specifies one of 8, 16, or 32 banks; the 12-bit address defines one of 4096 separate locations within the specified bank. Addresses written or compiled in the conventional manner reference consecutive banks and hence make most efficient use of the bank phasing feature.

CENTRAL MEMORY ACCESS

References to Central Memory from all areas of the system (Central Processor and Peripheral and Control Processors) go to a common address clearing house called a stunt box and are sent from there to all banks in Central Memory. The stunt box accepts addresses from the various sources under a priority system and at a maximum rate of one address every minor cycle. *Minor cycle=100 ns

An address is sent to all banks, and the correct bank, if free, accepts the address and indicates this to the stunt box. The associated data word is then sent to or stored from a central data distributor. The bank ignores the address if it is busy processing a previous address. The stunt box issues addresses at a maximum rate of one every minor cycle.

The stunt box saves, in a hopper mechanism, each address that it sends to Central Memory and then reissues it (and again saves it) under priority control in the event it is not accepted because of bank conflict. The address issue-save process repeats until the address is accepted, at which time the address is dropped from the hopper and the read or store data word is distributed. A fixed time lapse from address issue to the memory-accept synchronizes the action taken.

The hopper (i. e., a previously unaccepted address) has highest priority in issuing addresses to Central Memory. The Central Processor and Peripheral and Control Processors (all 10 share a common path to the stunt box) follow in that order.

A data distributor which is common to all processors handles all data words to and from Central Memory (the Peripheral and Control Processors share one read path and one write path to the distributor). A series of buffer registers in the distributor provides temporary storage for words to be written into storage when the addresses are not immediately accepted because of bank conflict.

Each group of four banks communicates with the distributor on separate 60-bit read and write paths, but only one word moves on the data paths at one time. However, words can move at minor cycle intervals between the distributor and Central Memory or distributor and address-sender.

Data words and addresses are correlated by control information (tags) entered in the stunt box with the address. The tags define the address sender, origin/ destination of data, and whether the address is a Read, Write, or Exchange Jump address.

MEMORY PROTECTION

All Central Processor references to Central Memory for new instructions, or to read and store data, are made relative to the Reference Address. The Reference Address defines the lower limit of a Central Memory program. Changes to the Reference Address permit easy relocation of programs in Central Memory.

During an Exchange Jump, an 18-bit Reference Address and an 18-bit Field Length (parts of the Exchange Jump package) are loaded into their respective registers to define the Central Memory limits of the program initiated by the Exchange Jump.

The relationship between absolute memory address, relative memory address, Reference Address (RA), and Field Length (FL) is indicated in Figure 2-1.

Figure 2-1. Memory Map

The following relationships must be true if the program is to operate within its bounds:

RA <= (RA + P) < (RA + FL) (Absolute Memory Addresses), or
0 <= P < FL (Relative Memory Addresses)

NOTE
  1. FL is the number of 60-bit words comprising the program, not an address.
  2. To avoid possible "artificial" range faults, instructions should not be stored near the upper limit address of the Field Length. For example, using absolute address [(RA + FL) - 1] for an instruction produces a range fault when the (look-ahead) Read Next Instruction occurs to (RA + FL). Data should always be stored in addresses near or approaching absolute location (RA + FL), rather than instructions.

An optional exit condition (EM in the Exchange Jump package) allows the Central Processor to stop on a memory reference outside the limits expressed above.

3. CENTRAL PROCESSOR

ORGANIZATION

The Central Processor is an extremely high-speed arithmetic processor which communicates only with Central Memory. It consists (functionally) of an arithmetic unit and a control unit. The arithmetic unit contains all logic necessary to execute the arithmetic, manipulative and logical operations. The control unit directs the arithmetic operations and provides the interface between the arithmetic unit and Central Memory. It also performs instruction fetching, address preparation, memory protection, and data fetching and storing.

The Central Processor is isolated from the Peripheral and Control Processors and is thus free to carry on high-speed computation unencumbered by input/output requirements.

The organization of the Central Processor in the 6400 system differs from the 6600 Central Processor in two important respects. The 6500 system has two Central Processors; each similar to the 6400 Central Processor. Central Processor differences are tabulated in Table 3-1.

TABLE 3-1. CENTRAL PROCESSOR. DIFFERENCES
SYSTEM INSTRUCTION REGISTERS ARITHMETIC SECTION
6400 and 6500 Central Processors Instruction Buffer Register; holds one 60-bit instruction word. Unified Arithmetic Section; executes instructions in serial order. Requires no reservation control.
6600 Central Processor Instruction Stack; holds eight 60-bit instruction words. Ten functional (arithmetic & logical) units; operate concurrently on unrelated instructions. Require reservation control.

The following discussion details the operation of the Central Processor in the 6600 system. With the exception of differences noted in the above table (and the inherent effects on Central Processor operation), the 6400 system Central Processor operation is identical, Each of the two 6500 Central Processors operates identically with the 6400 Central Processor.

Programs for the Central Processor are held in Central Memory. A program is begun by an Exchange Jump instruction from a Peripheral and Control Processor. This instruction also specifies a segment of Central Memory for the central program, specifies the mode of exit (normal or error) of the program, and sets initial quantities in the X, B, and A registers.

High speed in the Central Processor depends first on minimizing memory references. Twenty-four registers are provided to lower the Central Memory requirements for arithmetic operands and results. These 24 are divided into:

Eight 60-bit registers are provided to hold instructions (6600), thereby limiting the number of memory reads for repetitive instructions, especially in inner loops. Multiple banks of Central Memory are also provided to minimize memory reference time. References to different banks of memory may be handled without wait.

Speed of operation in a conventional computer is also limited by the serial manner in which instructions are executed; instructions are executed sequentially in time with little or no concurrency.

In the 6600 Computer System, this delay is minimized by providing 10 arithmetic (functional) units and a reservation control. Unrelated instructions are executed simultaneously, provided no conflicts exist in the arithmetic units.

The 6400 or 6500, with its unified arithmetic section, executes instructions serially, with little concurrency.

Programs are written for the Central Processor in a conventional manner, specifying a sequence of arithmetic and control operations to be executed. Each instruction in a program is brought up in its turn from one of the instruction registers. These registers are filled from Central Memory in a manner sufficient to keep a reasonable flow of instructions available. A branch to another area of the program voids the old instructions in the registers and brings in new instructions. When a new instruction is brought up, a test is made on it to determine which of the 10 arithmetic units is needed, if it is busy, and if reservation conflict is possible. If the unit is free and no conflict is present, the entire instruction is given to the specified arithmetic unit for further action. Another instruction may then be brought up for issuance.

The original sequence of the program is established at the time each instruction is issued. Only those operations which depend on previous steps prevent the issuing of instructions, and then only if the steps are incomplete. The reservation control keeps a running account of the address, increment, and operand registers and of the arithmetic units in order to preserve the original sequence.

On occasion, a program may use an Increment Store instruction to modify the contents of a memory location holding a subsequent instruction. In the 6600, this modification must occur before the instruction is read from Central Memory into the stack, for once in the stack the instruction can not be so modified. To avoid this potential problem, modification of any subsequent instruction words should be restricted to relative locations >_ (P) + 8. This rule applies equally to both "in-stack" loops and to other programs where, under certain conflict conditions, the Central Processor of the 6600 may continue reading instruction words from Central Memory while delaying execution of a previously issued Increment Store instruction.

Nearly all Central Memory references for information or instructions are made on an implicit or secondary basis. Instructions are fetched from memory only if the instruction registers are nearly empty (or when ordered by a branch). Information is brought to or from the operand registers only when appropriate address registers are referenced during the course of a program. Such references are also accounted for in the reservation control.

All Central Processor references to Central Memory are made relative to the lower boundary address assigned by a Peripheral and Control Processor. A Central Processor program may therefore be relocated in Central Memory by modifying the boundaries only. Any attempt by the Central Processor to reference memory outside of its boundaries causes an immediate exit which can be readily examined by a Peripheral and Control Processor and displayed for the operator.

The Exchange Jump instruction described on page 3-9 starts a central program. This instruction starts a sequence of Central Memory references which exchanges 16 words in memory with the contents of the address, increment, and operand registers of the Central Processor. Also exchanged are the program address, the Central Memory and Extended Core Storage boundaries, and choice of program exit. This instruction may be executed by any Peripheral and Control Processor and acts as an interrupt to an active central program as well as a start from an inactive state. The Exchange Jump is used by the operating system to switch between two central programs, leaving the first program in a usable state for later re-entry.

CENTRAL PROCESSOR PROGRAMMING

Central Processor program instructions are stored in Central Memory. A 60-bit memory location may hold 60 data bits, four 15-bit instructions, two 30-bit instructions or a combination of 15 or 30-bit instructions. Figure 3-1 shows all instruction combinations in a 60-bit word and the two instruction word formats.

The Central Processor reads 60-bit words from Central Memory and stores them in an instruction stack which is capable of holding up to eight 60-bit words.

Each instruction in turn is sent to a series of instruction registers for interpretation and testing and is then issued to one of 10 functional units for execution. The functional units obtain the instruction operands from and store results in the 24 operating registers. The reservation control records active operating registers and functional units to avoid conflicts and insure that the original instructions do not get out of order.

Functional Units

The 10 functional units in the 6600 system handles the requirements of the various instructions. The Multiply and Increment units are duplexed, and an instruction is sent to the second unit if the first is busy. The general function of each unit is listed in Table 3-2.

TABLE 3-2. FUNCTIONAL UNITS
UNIT GENERAL FUNCTION
Branch Handles all jumps or branches from the program.
Boolean Handles the basic logical operations of transfer, logical product, logical sum, and logical difference.
Shift Handles operations basic to shifting. This includes left (circular) and right (end-off sign extension) shifting, and Normalize, Pack, and Unpack floating point operations. The unit also provides a mask generator.
Add Performs floating point addition and subtraction on floating point numbers or their rounded representation.
Long add Performs one's complement addition and subtraction of 60-bit fixed point numbers.
Multiply Performs floating point multiplication on floating point numbers or their rounded representation.
Divide Performs floating point division of floating point quantities or their rounded representation. Also sums the number of "1's" in a 60-bit word.
Increment Performs one's complement addition and subtraction of 18-bit numbers.

Instruction Formats

Groups of bits in an instruction are identified by the letters f, m, i, j, k, and K (Figure 3-1). All letters represent octal digits except K,which is an 18-bit constant. The f and m digits are the operation code and identify the type of instruction. In a few instructions the i designator becomes a part of the operation code.

In most 15-bit instructions the i, j, and k digits each specify one of eight operating registers where operands are found and where the result of the operation is to be stored. In other 15-bit instructions, the j and k digits provide a 6-bit shift count.

In 30-bit instructions the i and j digits each specify one of eight operating registers where one operand is found and where the result is to be stored, and K is taken directly as an 18-bit second operand.

NOTE
In the 6600, it is permissible to pack the upper-order 15 bits (fmij portion) of a 30-bit instruction in the lower-order 15-bit portion of an instruction word. When this 30-bit instruction is executed, the lower-order 15-bits of K are taken from the upper-order 15 bits of the instruction word. In the 6400 and 6500, any 30-bit instruction with its fmij portion packed in the lower-order 15 bits of an instruction word will be executed as a STOP instruction.


Figure 3-1. Central Processor Instruction Formats

Operating Registers In order to provide a compact symbolic language, the 24 operating registers are identified by letters and numbers:

A = address register (A0, Al . . . A7)
B =increment register (B0, 131 . . . B7)
X =operand register (X0, X1 . . . X7)

The operand registers hold operands and results for servicing the functional units. Five registers (X1 - X5) hold read operands from Central Memory, and two registers (X6 - X7) hold results to be sent to Central Memory (Figure 3-2). Operands and results transfer between memory and these registers as a result of placing a quantity into a corresponding address register (Al - A7).

Placing a quantity into an address register A1 - A5 produces an immediate memory reference to that address and reads the operand into the corresponding operand register X1 - X5. Similarly, placing a quantity into address register A6 or A7 stores the word in the corresponding X6 or X7 operand register in the new address.

Figure 3-2. Central Processor Operating Registers

The increment instructions place a result in address register Ai (where "i" = 0 to 7) in three ways:

The A0 and X0 registers are independent and have no connection with Central Memory. They may be used for scratch pad or intermediate results. Note the special use of A0 and X0 when executing Extended Core Storage communication instructions.

The B registers have no connection with Central Memory. The BO register is fixed to provide a constant zero (18-bit) which is useful for various tests against zero, providing an unconditional jump modifier, etc. In general, the n registers provide means for program indexing. For example, B4 may store the number of times a program loop has been traversed, thereby providing a terminal condition for a program exit.

An Exchange Jump instruction from a Peripheral and Control Processor enters initial values in the operating registers to start Central Processor operation. Subsequent address modification instructions executed in the increment functional units provide the addresses required to fetch and store data.

Program Address
An 18-bit P register serves as a program address counter and holds the address for each program step. P is advanced to the next program step in the following ways:

  1. P is advanced by one when all instructions in a 60-bit word have been extracted and sent to the instruction registers.

  2. P is set to the address specified by a Go To . . . (branch) instruction. If the instruction is a Return Jump, (P) + 1 is stored before the branch to allow a return to the sequence after the branch.

  3. P is set to the address specified in the Exchange Jump package.

All branch instructions to a new program start the program with the instruction located in the highest order position of the 60-bit word.

Exchange Jump A Peripheral and Control Processor Exchange Jump instruction starts or interrupts the Central Processor and provides Central Memory with the first address (which is the address in the Peripheral and Control Processor A register) of a 16-word package in Central Memory. The Exchange Jump package (Figure 3-3) provides the following information on a program to be executed:

  1. Program address (P)
  2. Reference Address for Central Memory (RA CM )
  3. Field length of program for Central Memory (FLCM)
  4. Reference Address for Extended Core Storage (RAECS
  5. Field length of program for Extended Core Storage (FLECS)*
  6. Program exit mode (EM)
  7. Initial contents of the eight A registers
  8. Initial contents of the eight X registers
  9. Initial contents of B registers B1 - B7 (BO is fixed at 0)
*In the 6400 and 6500 the upper three bits of RA(ECS) are not transferred to the RA(ECS) register.

Figure 3-3. Exchange Jump Package

The Central Processor enters the information about a new program into the appropriate registers and stores the corresponding and current information from the interrupted program at the same 16 locations in Central Memory. Hence, the controlling information for two programs is exchanged. A later Exchange Jump may return an interrupted program to the Central Processor for completion. The normal relation of the A and X registers (described earlier) is not active during the Exchange Jump so that the new entries in A are not reflected into changes in X.

PROGRAMMING NOTE

When an Exchange Jump interrupts the Central Processor, several steps occur to insure leaving the interrupted program in a usable state for re-entry:

  1. Issue of instructions halts after issuing all instructions from the current instruction word in the instruction stack.

  2. The Program Address register, P, is set to the address of the next instruction word to be executed.

  3. The issued instructions are executed, and then

  4. The parameters for the two programs are exchanged.
A subsequent Exchange Jump can then re-enter the interrupted program at the point it was interrupted, with no loss of program continuity.

To preserve the integrity of an "in-stack" loop (in the event of an Exchange Jump), it is illegal to modify the contents of any memory address which holds an executable instruction (or instruction word) contained within the loop.

EXAMPLE:

After executing the lower instruction at [Y + 3], the contents of memory location [Y + 1] differ from the contents of [Y + 1] in the stack. If the Exchange Jump comes in as indicated, subsequent reentry will call up the modified loop from memory, rather than the stack loop in its original un-modified form.

All Central Processor references to Central Memory for new instructions, or to fetch and store data, are made relative to the Reference Address. This allows easy relocation of a program in Central Memory. The Reference Address or beginning address and the Field Length define the Central Memory limits of the program. An Exit Selection allows the Central Processor to stop on a memory reference outside these limits.

The Program Address register P defines the location of a program step within the limits prescribed. Each reference to memory to fetch instructions is made to the address specified by P + RA. Hence program relocation is conveniently handled through a single change to RA.

A P = 0 condition specifies address zero and hence RA. This address is reserved for recording program exit (error) conditions and should not, therefore, be used to store data or instructions of a program.

Exit Mode


The Exit mode feature allows the programmer to select Exit or Stop conditions for the Central Processor. Exit selections are loaded into bits 36-53 of memory location "n+3" of the Exchange Jump package (Figure 3-3). When the Exchange Jump occurs to that package, the exit selections are stored in the Central Processor and the exit occurs as soon as the selected condition is sensed. The Exit conditions, as stored in bits 36-53 of address "n+3" in the Exchange Jump package, are shown below in octal format:
EM = 000000 Disable Exit mode - no Exit selections made.
EM = 010000 Address out of range -
  1. an attempt to reference either Central Memory or Extended Core Storage outside established limits, or
  2. the word count, [ (Bj) + K , in an Extended Core Storage Communication instruction is negative.
(For details on action when an address is out of range, refer to the Increment and Extended Core Storage instruction descriptions. )
EM = 020000 Operand out of range - floating point arithmetic unit received an infinite operand (see Range Definitions under Floating Point Arithmetic following).
EM = 030000 Address or operand out of range
EM = 040000 Indefinite operand - floating point arithmetic unit (Add, Multiply, or Divide) attempted to use an indefinite operand (see Range Definitions, page 3-17).
EM = 050000 Indefinite operand or address out of range
EM = 060000 Indefinite operand or operand out of range
EM = 070000 Indefinite operand or operand or address out of range

Typically, the Reference Address (RA) for any program is left cleared to all zeros. When an error exit is taken, the Central Processor records at RA the exit condition (upper 2 octal digits only) and the Program Address at exit time (refer to the format below).

NOTE

The Exit condition(s) recorded at RA comprises all the Exit conditions detected since the last Exchange Jump, regardless of whether they were selected. Thus, combinations of error Exit conditions (03, 05, 06 or 07) can appear at RA:

  1. When at least one Exit condition was selected and the selected condition plus another condition occurred since the last Exchange Jump, or

  2. When more than one Exit condition was selected and each occurred in the same minor cycle.
The contents of RA are then read up, interpreted as a Stop instruction, and the Central Processor stops.

For error stops, (P) + 1 gives only an approximate location of the error since the Central Processor may have issued other instructions to the functional units (one of which may have been a branch) before the exit was sensed.

On an Address Out of Range, hardware action differs from that outlined above. In some cases, a stop occurs when an address is out of bounds even though an Exit mode stop is not selected for this condition. Table 3-3 summarizes hardware action for operations which may reference addresses that are out of bounds.

TABLE 3-3. EXIT MODE: ADDRESS OUT OF BOUNDS
.
HARDWARE ACTION
OPERATION EXIT MODE SELECTED EXIT MODE NOT SELECTED
RNI to an address that is out-of bounds (occurs when an instr. is located in absolute address (RA + FL) - 1).
  1. Detect error condition
  2. Clear P
  3. Stop by reading(AAZ)
  4. Write EM and (P) + 1 into RA
  1. Detect error condition
  2. Stop by reading (AAZ)
  3. Nothing stored in RA
  4. (P) = out of range P or (P) + 1
Branch to an address that is out-of-bounds.
  1. Detect error condition
  2. Clear P
  3. Stop by reading (AAZ)
  4. Write EM and jump address + 1 in RA
  1. Detect error condition
  2. Stop by reading (AAZ)
  3. Nothing stored in RA
  4. (P) = out of range P or (P)+1
Read Operand
  1. Detect error condition
  2. Clear P
  3. Stop by reading (AAZ)
  4. Write EM and (P) + 1 into RA
  5. (Xi) = (AAZ)
  1. Detect error condition
  2. Read (AAZ) into Xi
  3. Continue program
Write Operand
  1. Detect error condition
  2. Clear P
  3. Stop by reading (AAZ)
  4. Write EM and (P) + 1 into RA
  1. Detect error condition
  2. Read (AAZ) , but (Xi) not stored; (Xi) and (Ai) unchanged.
  3. Continue program

Action After Exit Mode or Normal Stop
Typically, a Peripheral and Control Processor periodically searches for an unchanging Central Processor Program Address register (any value) to determine if the Central Processor has stopped. Once it has been determined that the Central Processor has stopped, the examining Peripheral and Control Processor can transfer control to an error routine to determine the nature of the condition causing the Stop. Figure 3-4 illustrates sample steps for processing Central Processor stops (either Exit mode or normal).


Figure 3-4. Detecting and Handling Central Processor Stops

Floating Point Arithmetic

Format
Floating point arithmetic takes advantage of the ability to express a number with the general expression kBn where:

k = coefficient
B = base number
n = exponent, or power to which the base number is raised

The base number is constant (2) for binary-coded quantities and is not included in the general format. The 60-bit floating-point format is shown below. The binary point is considered to be to the right of the coefficient, thereby providing a 48-bit integer coefficient, the equivalent of about 14 decimal digits. The sign of the coefficient is carried in the highest order bit of the packed word. Negative numbers are represented in one's complement notation.

The 11-bit exponent carries a bias of 210 (20008) when packed in the floating point word (biased exponent sometimes referred to as characteristic). The bias is removed when the word is unpacked for computation and restored when a word is packed into floating format. Table 3-4 lists (in decimal and octal notation) the complete range of permissible exponents and the octal form of the corresponding positive and negative floating point words.

Thus, a number with a true exponent of 342 would appear as 2342; a number with a true exponent of -160 would appear as 1617. Exponent arithmetic is done in one's complement notation. Floating point numbers can be compared for equality and threshold.

TABLE 3-4. RANGE OF PERMISSIBLE EXPONENTS


Normalizing and Rounding
Normalizing a floating point quantity shifts the coefficient left until the most significant bit is in bit 47. Sign bits are entered in the low-order bits of the coefficient as it is normalized. Each shift decreases the exponent by one.

A round bit is added (optionally) to the coefficient during an arithmetic process and has the effect of increasing the absolute value of the operand or result by one-half the value of the least significant bit. Normalizing and rounding are not automatic during pack or unpack operations so that operands and results may not be normalized.

Single and Double Precision
The floating point arithmetic instructions generate double-precision results. Use of unrounded operations allows separate recovery of upper and lower half results with proper exponents; only upper half results can be obtained with rounded operations.

Double length registers appear as follows:

Range Definitions
A result with an exponent so large that it exceeds the upper limit of octal 3777 (overflow case) is treated as an infinite quantity. A coefficient of all zeros and an exponent of octal 3777 or 4000 is packed for this case. An optional exit is provided when an attempt is made to use an infinite operand in the floating arithmetic units since its use may propagate an indefinite result as shown in Table 3-5. No error exit occurs when an infinite or indefinite result is generated in a functional unit.

TABLE 3-5. INDEFINITE FORMS

A result the exponent of which is less than the lower limit of octal 0000 (underflow case) is treated as a zero quantity. This quantity is packed with a zero exponent and zero coefficient. No exit is provided for underflow. A result with an exponent of octal 0000 and a coefficient which is not zero is a non-zero quantity and is packed with a zero exponent and the non-zero coefficient.

Use of either infinity or zero as operands may produce an indefinite result. An exponent of octal 1777 and a zero coefficient are packed in this case, and an optional exit provided. Note that zero, infinite, and indefinite results are generated or regenerated in floating arithmetic operations only. The branch instructions test for infinite or indefinite quantities.

In all floating arithmetic operations, an attempt to normalize an indefinite quantity returns the original quantity, e. g., if the number 17770237. . . were to be normalized, the result would be the same as the original number. Note that Exit mode does not occur on detecting an indefinite quantity in the Shift Unit.

Exit mode tests for infinite and indefinite operands are made only in the Floating Add, Multiply, and Divide Units. The 12 most significant bits of each operand are tested for these special forms.

In the Multiply and Divide Units (but not in the Floating Add Unit) there is a special test for zero operands as determined by the 12 most significant bits.

Thus the special operand forms (in octal) are:

Whenever infinite, indefinite, or zero results are generated in accordance with the rules given in Table 3-5 and Appendix C, only the following octal words can occur as results:

Note that in these cases the 48 least significant bits of the result are zeros. Indefinite and zero results generated in accordance with Table 3-5 and Appendix C are always positive, but the sign of infinite results is determined by the usual algebraic sign convention. For example:

There is no special treatment of zero operands in the Floating Add unit. Zero coefficients and the forms 0000X. . . X and 7777X. . . X are not specially detected, and unstandardized zero results can be produced. (See description of 30 instruction, page 3-37. )

Overflow and Underflow
Exponents lying outside the range -17778 to +17778 cannot be generated during execution of a floating point arithmetic instruction or during execution of a Normalize instruction. An attempt to generate an exponent greater than +17778 yields an infinite result (overflow case). An attempt to generate an exponent less than -17778 yields a zero result (underflow case). All cases of overflow and underflow are listed in Table 3-6.

Converting Integers to Floating Format
Conversion of integers to floating point format makes use of the Shift Unit and the zero constant in increment register B0. The B0 quantity provides for generation of exponent bias in this case. For example, the instructions:

form an 18-bit signed integer in operand register X2 as a result of the addition of the contents of increment registers B3 and B4. The integer coefficient with its sign, plus the octal 2000 exponent is then packed into the floating format shown earlier. The coefficient is not normalized; normalizing may be accomplished with a Normalize instruction.

Note 1. Overflow of Upper Sum: Overflow cannot occur unless one operand is infinite. In this case the result is as indicated. If a one-place Right Shift occurs when the larger operand exponent is equal to +17768, a correct result with exponent +17778 is generated.

Note 2. Underflow of Exponent During Normalization: The final (Bj) are the same as if underflow had not occurred. In particular, if the initial coefficient is zero, (Bj) are equal to 608.

Fixed Point Arithmetic

Fixed point addition and subtraction of 60-bit numbers are handled in the Long Add Unit (6600). Negative numbers are represented in one's complement notation, and overflows are ignored. The sign bit is in the high-order bit position (bit 59) and the binary point is at the right of the low-order bit position (bit 0).

The Increment Units provide an 18-bit fixed point add and subtract facility. Negative numbers are represented in one's complement notation and overflows are ignored. The sign bit is in the high-order bit position (bit 17), and the binary point is at the right of the low-order bit position (bit 0). The Increment Units allow program indexing through the full range of Central Memory addresses.

Fixed point integer addition and subtraction are possible in the Floating Add Unit providing the exponents of both operands are zero and no overflow occurs. The unit performs the one's complement addition (or subtraction) in the upper half of a 98-bit accumulator. If overflow occurs, the unit shifts the result one place right and adds one to the exponent, thereby producing a floating point quantity. Thus, care must be used in performing fixed point arithmetic in the Floating Add Unit.

Fixed point integer multiplication is handled in the multiply functional units as a subset operation of the unrounded Floating Multiply (40, 42) instructions. The multiply is double precision (96 bits) and allows separate recovery of upper and lower products. The multiply requires that both of the integer operands be converted (by program) to floating format to provide biased exponents. This insures that results are not sensed as underflow conditions. The bias is removed when the result is unpacked.

An integer divide takes several steps and makes use of the Divide and Shift Units. For example, an integer quotient X1 = X2/X3 is produced by the following steps:
.
Instructions
Remarks
1) Pack X2 from X2 and BO Pack X2
2) Pack X3 from X3 and BO Pack X3
3) Normalize X3 in X0 and BO Normalize X3 (divisor)
4) Floating quotient of X2 and X0 to X1 Divide
5) Unpack X1 to X1 and B7 Unpack quotient
6) Shift X1 nominally left B7 places Shift to integer position
The divide requires that:
. 1) both integer (247 maximum) operands be in floating format
and 2) the divisor be shifted 48 places left
or 3) the quotient be shifted 48 places right
or 4) any combination of n left-shifts of the divisor and 48-n right shifts of the quotient be accomplished.
The Normalize X3 instruction shifts the divisor n places left (n >= 0), providing a divisor exponent of -n. The quotient exponent then is: 0 - (-n) - 48 = n - 48 <= 0. After unpacking and shifting nominally left, the negative (or zero) value in B7 shifts the quotient 48 - n places right; producing an integer quotient in X1. A remainder may be obtained by an integer multiply of X1 and X3 and subtracting the result from X2.

Description of Central Processor Instructions

This section describes the Central Processor instructions. Instruction grouping follows a somewhat pedagogical approach (i.e., simple to complex) and does not necessarily relate instructions to the functional units (6600 system) which execute them. Central Processor instructions as related to functional units are tabulated in Appendix B, Instruction Execution Times.

TABLE 3-7. CENTRAL PROCESSOR INSTRUCTION DESIGNATORS
DESIGNATOR
USE
A
Specifies one of eight 18-bit address registers.
B
Specifies one of eight 18-bit index registers; BO is fixed and equal to zero.
fm
A 6-bit instruction code.
i
A 3-bit code specifying one of eight designated registers (e.g., Ai).
j
A 3-bit code specifying one of eight designated registers (e. g. , B j).
jk
A 6-bit constant, indicating the number of shifts to be taken.
k
A 3-bit code specifying one of eight designated registers (e.g., Bk).
K
An 18-bit constant, used as an operand or as a branch destination (address).
X
Specifies one of eight 60-bit operand registers.

Preceding the description of each instruction is the octal code, mnemonic code and address field, the instruction name and length. Mnemonic codes and address field mnemonics are from ASCENT, a Central Processor Assembly language. The equivalent COMPASS mnemonics are given in Appendix D.

EXAMPLE:

12 BXi Xj+Xk Logical Sum of Xj and Xk to Xi (15 bits)
Octal
Code
Mnemonic
Code
Address
Field
Instruction Name Instruction
Length

Instruction formats are also given; parallel lines within a format indicate these bits are not used in the operation.


Program Stop and No Operation
00 PS . Program Stop (30 Bits)

This instruction stops the Central Processor at the current step in the program. An exchange Jump is necessary to restart the Central Processor.


46 NO . No operation (Pass) (15 Bits)

This instruction is a "do-nothing" instruction that is typically used to pad the program between certain program steps.
EXAMPLE:

In this example, a Pass instruction is used to pad the remainder of the word at P. Since the next instruction is 30 bits, it cannot fit in P and must be placed in P + 1.


Increment
50 SAi Aj + K Set Ai to Aj + K (30 Bits)
51 SAi Bj + K Set Ai to Bj + K (30 Bits)
52 SAi X j + K Set Ai to X j + K (30 Bits)

53 SAi Xj + Bk Set Ai to Xj + Bk (15 Bits)
54 SAi Aj + Bk Set Ai to Aj + Bk (15 Bits)
55 SAi Aj - Bk Set Ai to Aj - Bk (15 Bits)
56 SAi Bj + Bk Set Ai to Bj + Bk (15 Bits)
57 SAi Bj - Bk Set Ai to Bj - Bk (15 Bits)

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18- bit result in address register i. Overflow, in itself, is ignored, but an address range fault may result from overflow in this set of instructions.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word. Note that an immediate memory reference is performed to the address specified by the final content of address registers A1 - A7. The operand read from memory address specified by Al - A5 is sent to the corresponding operand register X1 - X5. When A6 or A7 is referenced, the operand from the corresponding X6 or X7 operand register is stored at the address specified by A6 or A7.

NOTE

If, in this category of instructions, the result placed in address register Ai is an address out of range, the following occurs: (Note that this action is independent of an Exit selection on Address Out of Range.) If i = 1-5: Operand register Xi is loaded with the contents of absolute address zero and the contents of memory location (Ai) are unchanged. If i = 6 or 7: Operand register Xi retains its original contents and the contents of memory location (Ai) are unchanged.
EXAMPLE:				Initial Quantities:
   50  SAi     Aj + K	i = 4	K = 2345678
       SA4     A6 + K	j = 6	A4 = 3211108
       SA4 = 4321008 +	2345678	A6 = 4321008
       SA4 = 6666678	X4 = 00.....008
                      Storage location 666667 = 7. . . 753421046008
                      Final Quantities:
                      A4 = 6666678
                      A6 = 4321008
                      X4 = 7. .. 753421046008
60 SBi Aj + K Set Bi to Aj + K (30 Bits)
61 SBi Bj + K Set Bi to Bj + K (30 Bits)
62 SBi Xj + K Set Bi to Xj + K (30 Bits)

63 SBi Xj + Bk Set Bi to X j + Bk (15 Bits)
64 SBi Aj + Bk Set Bi to Aj + Bk (15 Bits)
65 SBi Aj - Bk Set Bi to Aj - Bk (15 Bits)
66 SBi Bj + Bk Set Bi to Bj + Bk (15 Bits)
67 SBi Bj - Bk Set Bi to Bj - Bk (15 Bits)

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18-bit result in increment register Bi. An overflow condition is ignored.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word.
70 Six Aj + K Set Xi to Aj + K (30 Bits)
71 SXi Bj + K Set Xi to Bj + K (30 Bits)
72 SXi Xj + K Set Xi to Xj + K (30 Bits)

73 SXi Xj + Bk Set Xi to Xj + Bk (15 Bits)
74 SXi Aj + Bk Set Xi to Aj + Bk (15 Bits)
75 SXi Aj - Bk Set Xi to Aj - Bk (15 Bits)
76 SXi Bj + Bk Set Xi to Bj + Bk (15 Bits)
77 SXi Bj - Bk Set Xi to Bj - Bk (15 Bits)

These instructions perform one's complement addition and subtraction of 18-bit operands and store an 18-bit result into the lower 18 bits of operand register Xi. The sign of the result is extended to the upper 42 bits of operand register Xi. An overflow condition is ignored.

Operands are obtained from address (A), increment (B), and operand (X) registers as well as the instruction itself (K = 18-bit signed constant). Operands obtained from an Xj operand register are the truncated lower 18 bits of the 60-bit word. EXAMPLE:

					Initial Quantities:
	73	SXi	Xj + Bk	i = 2	X2 = 0. . . 07453214028
		SX2	X3 + B1	j = 3, K = 1	X3 = 0_ . . 06522243108
		SX2 =	0. . . 06522243108 + 5112458   B1= 5112458
		SX2 =	7. . . 77777355558
					Final Quantities:
                              X2 = 7...77777355558
                              X3 = 0...06522243108
                              B1 =         5112458


Fixed Point Arithmetic
36 IXi Xj +Xk Integer sum of Xj and Xk to Xi (15 Bits)

This instruction forms a 60-bit one's complement sum of the quantities from operand registers Xj and Xk and stores the result in operand register Xi. An overflow condition is ignored.

37 IXi Xi - Xk Integer difference of Xj and Xk to Xi (15 Bits)

This instruction forms the 60-bit one's complement difference of the quantities from operand registers Xj (minuend) and Xk (subtrahend) and stores the result in operand register Xi. An overflow condition is ignored.

47 CXi Xk Count the number of "1's" in Xk to Xi (15 Bits)

This instruction counts the number of "1 's" in operand register Xk and stores the count in the lower order 6 bits of operand register Xi. Bits 6 through 59 are cleared to zero.





















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