A Mechanized Refinement Framework for Analysis of Custom Memories

S. Ray and J. Bhadra

In J. Baumgartner and M. Sheeran, editors, Proceedings of the 7th International Conference on Formal Methods in Computer-aided Design (FMCAD 2007), Austin, TX, November 2007, pages 239-242. IEEE Computer Society

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Abstract

We present a framework for formal verification of embedded custom memories. Memory verification is complicated by the difficulty in abstracting design parameters induced by the inherently analog nature of transistor-level designs. We develop behavioral formal models that specify a memory as a system of interacting state machines, and relate such models with an abstract read/write view of the memory via refinements. The operating constraints on the individual state machines can be validated by readily available data from analog simulations. The framework handles both static RAM (SRAM) and flash memories, and we show initial results demonstrating its applicability.

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BibTex

@Inproceedings{ray-mechanized,
  author    = "S. Ray and J. Bhadra",
  title     = "{A Mechanized Refinement Framework for Analysis of Custom Memories}",
  editor    = "J. Baumgartner and M. Sheeran",
  booktitle = "{Proceedings of the $7$th International Conference on 
                Formal Methods in Computer-Aided Design (FMCAD 2007)}",
  address   = "{Austin, TX}",
  month     = nov,
  pages     = "239-242",
  year      = 2007,
  publisher = "IEEE Computer Society"
}