I am going to finish my PhD in the Department of Computer Sciences at UT Austin. My advisor is Dr. Calvin Lin. More details of my research are here. Here's my resume as of July 2016.
A list of the graduate courses that I enjoyed
Graduate courses at UT
Graduate courses at IIT Madras
For this project, we designed and implemented an in-order micro-architecture with 10ns cycle time for a subset of the x86 instruction set. This included a detailed design of the core pipeline, caches, main-memory and the I/O devices. The entire design was implemented at the gate-level in Verilog. Getting all the subsystems to work together in sync was a key challenge of this project. We experimented with various cache organizations, branch predictor and pre-fetcher designs to improve the performance of our pipeline.
For this project, I simulated a reinforcement learning algorithm in hardware for packet routing in an on-chip network. The algorithm has been successful for network routing, and the key challenge of the project was to make it feasible and cost-efficient to be implemented in hardware. The preliminary results from a study of the latency and cost trade-offs of the proposed approach were very encouraging. I plan on working on improving the current algorithm to reduce the hardware costs and further improve routing performance.
We explored relevant program features for building a machine learning based approach to determine loop tiling parameters. We also built, trained and analyzed a neural network predictor to find an efficient loop tiling configuration for a few simple programs.