ARDAVAN PEDRAM

email: Perdavan at Stanford dot edu

Office: Gates 312

 

Resume

 

 

Description: Macintosh SSD:Users:ardavan:Pictures:iPhoto Library:Previews:2014:09:12:20140912-195948:7GPhoDDFQ4ulWfKgFP8XuA:ardi_pic2.jpg

 

 

 

Postdoctoral Research Scholar

Department of Electrical Engineering

Stanford University

 

I am a member of the VLSI Research Group working with Professor Mark Horowitz.

I am also a member of the FLAME group collaborating with my PhD supervisors professors Robert van de Geijn and Andreas Gerstlauer.

 

I received my PhD in Computer Engineering from the department of Electrical and Computer Engineering at The University of Texas at Austin.

My research is in High performance computing and Computer architecture.

I specifically work on hardware-software co-design (algorithm for architecture) of special purposed accelerators for high performance linear algebra and signal processing applications.

 


 

Dissertation:

 

“Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics”

 

Download the PDF

Poster: TCPP Best Poster Award in IPDPS 2013 conference PhD Forum

Award: National Science Foundation (NSF) Grant

 

 


 

Tools:

 

A basic version of the Linear Algebra Core (LAC) cycle accurate simulator with General Matrix Matrix Multiplicatin (GEMM) and Cholesky factorization functionality will soon be released under free BSD license.

The simulator engine is also functional and performs the actual computations on the simulated hardware. Therefore, debugging under this environment is easy.

 


 

Refereed Publications:

 

1-      Ardavan Pedram, John McCalpin, and Andreas Gerstlauer:

A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores,

To appear in The Journal of Signal Processing Systems, Springer, 2014.

 

2-      Ardavan Pedram, Andreas Gerstlauer, and Robert van de Geijn:

"Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator,"

IEEE Transactions on Computers (TC) Special Section on Computer Arithmetic, August 2014.

 

3-      Ardavan Pedram, John McCalpin, and Andreas Gerstlauer:

Transforming a Linear Algebra Core to an FFT Accelerator,”

The 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP2013).

 

4-      Ardavan Pedram, Andreas Gerstlauer, and Robert van de Geijn:

"Floating Point Architecture Extensions for Optimized Matrix Factorization,"

The 21st IEEE International Symposium on Computer Arithmetic (ARITH21).

 

5-      Ardavan Pedram, Robert van de Geijn, and Andreas Gerstlauer:

"Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures,"

IEEE Transactions on Computers (TC) Special Issue on Energy Efficient Computing, Volume 61, Issue 12, Page(s) 1724 – 1736, December 2012. 

 

6-      Ardavan Pedram, Andreas Gerstlauer, and Robert van de Geijn:

"On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators,"

The 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2012). (Acceptance rate 28%)

 

7-      Ardavan Pedram, Syed Gilani, Nam Sung Kim, Robert van de Geijn, Mike Schulte,and Andreas Gerstlauer:

"A Linear Algebra Core Design For Efficient Level-3 BLAS,"

The 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP2012).

 

8-      Ardavan Pedram, Andreas Gerstlauer, and Robert van de Geijn:

"A High-performance, Low-power Linear Algebra Core,"

The 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP2011). (Acceptance rate 25%)

 

9-      Ardavan Pedram, David Craven, and Andreas Gerstlauer:

"Modeling Cache Effects at the Transaction Level,"

International Embedded Systems Symposium (IESS2009). (Best paper runner-up)

 

10-   Ardavan Pedram, Mohammad Reza Jamali, Caro Lucas, and Syed Mehdi Fakhraie:

"Local Linear Model Tree (LOLIMOT) Reconfigurable Parallel Hardware,"

Transactions on Engineering, Computing and Technology, Volume 13, Page(s) 96-101, May 2006.

 


 

Pictures