Research
I am a PhD student in the Department of Computer Sciences at the University of Texas. I am a member of the Computer Architecture and Technology Laboratory (CART) in the Department of Computer Sciences and the Satellite Design Laboratory (SDL) in the Department of Aerospace Engineering.
As a part of CART, I am the principal developer of the C/Fortran compiler for the TRIPS prototype processor. My dissertation research focuses on compilation techniques for distributed micro-architectures, exploiting ILP, dataflow execution and predication.
In the Satellite Design Laboratory, I develop the the control and data handling (CNDH) software for two nano-satellites as part of the FASTRAC project. The CNDH coordinates the various hardware subsystems on the satellites (radio, gps, thruster, power) and runs experiments autonomously. The satellites are scheduled to launch in 2009.
Select Publications
- Dataflow Predication (MICRO 2006)
- Merging Head and Tail Duplication with Convergent Hyperblock Formation (MICRO 2006)
- Compiling for EDGE Architectures (CGO 2006)
- TRIPS Application Binary Interface (UTCS Tech Report TR-05-22)
- TRIPS Intermediate Language Manual (UTCS Tech Report TR-05-20)
- Scaling to the End of Silicon with EDGE Architectures (IEEE Computer, July 2004)
Current and Past Projects
- The Tera-op Reliable Intelligently adaptive Processing System (TRIPS)
- FASTRAC - The University of Texas Nanosatellite Program
- Quazal Net-Z for Sony PlayStation 2 v1.0
- Metrowerks/Freescale CodeWarrior for Sega Dreamcast v1.0
- Metrowerks/Freescale CodeWarrior for Hitachi SuperH v1.0/2.0
- Metrowerks/Freescale CodeWarrior for Motorola M*CORE v1.5/v2.0