Boris Grot. Photo by Yume Grot.
 

Boris Grot

Ph.D. Student
Computer Science
University of Texas at Austin
bgrot@cs.utexas.edu
 

 


Publications

 

REFEREED CONFERENCE PUBLICATIONS

Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees.
B. Grot, J. Hestness, S. W. Keckler and O. Mutlu. The 38th International Symposium on Computer Architecture (ISCA), 2011.
Acceptance rate: 19%

Reducing Network-on-Chip Energy Consumption through Spatial Locality Speculation.
H. Kim, P. Ghoshal, B. Grot, P. Gratz and D. Jimenez. The Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 2011.
Acceptance rate: 25%

Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-a-Chip.
B. Grot, S. W. Keckler and O. Mutlu. The 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009.
Acceptance rate: 25%

Express Cube Topologies for On-Chip Interconnects.
B. Grot, J. Hestness, S. W. Keckler and O. Mutlu. The 15th International Symposium on High Performance Computer Architecture (HPCA), 2009.
Acceptance rate: 19%

Regional Congestion Awareness for Load Balance in Networks on a Chip.
P. Gratz, B. Grot and S. W. Keckler. The 14th International Symposium on High Performance Computer Architecture (HPCA), 2008.
Acceptance rate: 20%

 

REFEREED WORKSHOP PUBLICATIONS

Netrace: Dependency-Driven Trace-Based Network-on-Chip Simulation.
J. Hestness, B. Grot, S. W. Keckler. 3rd International Workshop on Network on Chip Architectures (NoCArc), 2010.

Topology-aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors.
B. Grot, S. W. Keckler and O. Mutlu. 6th Annual Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), 2010.

Segment Gating for Static Energy Reduction in Networks-On-Chip.
K. C. Hale, B. Grot and S. W. Keckler. 2nd International Workshop on Network on Chip Architectures (NoCArc), 2009.

Scalable On-chip Interconnect Topologies.
B. Grot and S. W. Keckler. 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), 2008.

Good Memories: Enhancing Memory Performance for Precise Flow Tracking.
B. Grot and W. Mangione-Smith. Advanced Networking and Communications Hardware Workshop (ANCHOR), 2005.

 

TOOL RELEASES

Ocin_tsim: a DVFS-aware simulator for NoC based platforms.
S. Prabhu, B. Grot, P. V. Gratz and J. Hu. 1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1), 2009.