Changkyu Kim

Changkyu Kim

Publications || Internship || Patent || Presentations || Education || Experience

PhD. Student
Department of Computer Sciences
The University of Texas at Austin
Email: ckkim(at)cs.utexas.edu

Research Interests

High performance computer architecture, scalable and distributed processor architecture, memory subsystem and power-efficient computing. My past work includes novel level-2 cache designs (called NUCA - Non-Uniform access Cache Architecture) for future technologies and VLSI implementation of the on-chip network and the secondary memory system in the TRIPS processor

Currently, I am working on the TRIPS (The Tera-Op Reliable Intelligently adaptive Processing System) project with the CART group under Dr. Doug Burger and Dr. Steve Keckler

Publications

A NUCA Substrate for Flexible CMP Cache Sharing
Jaehyuk Huh, Changkyu Kim , Hazim Shafi, Lixin Zhang, Doug Burger, and Stephen W. Keckler
IEEE Transactions on Parallel and Distributed Systems (TPDS), Special Issue on CMP Architecture, Auguest 2007.

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, , H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P.K. Shivakumar, S. W. Keckler, D.C. Burger
The 36th International Symposium on Microarchitecture (MICRO), December 2006.
Implementation and Evaluation of On-Chip Network Architectures
Paul Gratz, Changkyu Kim , Robert McDonald, Doug Burger, and Stephen W. Keckler
The 24th International Conference on Computer Design (ICCD), October 2006.
A NUCA Substrate for Flexible CMP Cache Sharing
Jaehyuk Huh, Changkyu Kim , Hazim Shafi, Lixin Zhang, Doug Burger, and Stephen W. Keckler
The 19th ACM International Conference on Supercomputing (ICS), June 2005.
Scaling to the End of Silicon with EDGE Architectures
D. Burger, S.W. Keckler, K.S. McKinley, M. Dahlin, L.K. John, C. Lin, C.R. Moore, J. Burrill, R.G.McDonald, W. Yoder, and the TRIPS Team
IEEE Computer, July 2004.
TRIPS: A Polymorphous Architecture for Exploiting ILP, TLP, and DLP
Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, D. Burger, S.W. Keckler, R.G. McDonald, and C.R. Moore.
ACM Transactions on Architecture and Code Optimization (TACO), March 2004.
(Extended version of our ISCA 2003 TRIPS paper)
NUCA: A Non-Uniform Cache Access Architecture for Wire-Delay Dominated On-Chip Caches
Changkyu Kim, D.C. Burger and S.W. Keckler.
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, Nov.-Dec. 2003.
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D.C. Burger, S.W. Keckler, and C.R. Moore
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, Nov.-Dec. 2003.
Exploiting ILP, DLP, and TLP Using Polymorphism in the TRIPS Architecture
K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D.C. Burger, S.W. Keckler, and C.R. Moore
30th International Symposium on Computer Architecture (ISCA), June 2003.
An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches
Changkyu Kim, D.C. Burger and S.W. Keckler.
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X) , October 2002.
An Adaptive Cache Structure for Future High-Performance Systems
Changkyu Kim, D.C. Burger and S.W. Keckler.
IBM Austin CAS Center for Advanced Studies Conference, February 2002.

Internship

Microprocessor Technology Laboratory (MTL), Intel Corp., Santa Clara, CA (05/2006 - 08/2006)
- High-Performance Chip Multi-Processor (CMP) Memory Systems for Many-Core Architecture
- Supervisor: Dr. Pradeep Dubey

Patent

Non-Uniform Cache Apparatus, Systems, and Methods
With D.C. Burger and S.W. Keckler. U.S. patent #6965969, assigned 11/15/05

Invited and Conference Presentations

TRIPS Secondary Memory System

Intel - Santa Clara, CA, May, 2006

TRIPS Tutorial at HPCA 2006
- Austin, TX, Feb, 2006
TRIPS Tutorial at ISCA 2005
- Madison, WI, June, 2005
TRIPS
- Samsung Electronics - Korea, Dec, 2004
NUCA
- Intel - Shrewsbury, MA, Jan 2003
- HP/Compaq - Marlboro, MA, Jan 2003
- Samsung Electronics - Korea, Dec, 2002
- ASPLOS-X - San Jose, CA, Oct, 2002
- IBM Austin CAS Workshop - Austin, TX, Jan, 2002

Education

Ph.D. student in Computer Sciences at The University of Texas at Austin, U.S.A., since Aug 2000.
M.S. in Engineering at Department of Computer Engineering, Seoul National University, Korea, Feb 1999.
B.S. in Engineering at Department of Computer Engineering, Seoul National University, Korea, Feb 1997.

Professional Experience

University of Texas at Austin
- Research Assistant (Summer 2001 - present)
- Teaching Assistant for Introduction to VLSI Design (Spring 2001)
- Teaching Assistant for Computer Organization and Programming (Fall 2000)

LG-CIT (LG Corporate Institute of Technology)
- Research Engineer (01/1999 ~ 03/2000)
  - A single Chip HDTV Down-Conversion Decoder Project (01/1999 ~ 04/1999)
    : Implementing interface logic with Philips PCI controller.
  - A single Chip HDTV Full-Conversion Decoder Project (05/99 ~ present) :
    : Implementing of MPEG2 bit stream parser, Fabricated in a CMOS 0.25um.

RIACT (Research Institute Of Advanced Computer Technology), Seoul National University
- Research Assistant (03/1997 ~ 02/1999)
  - Performance analysis of Ring-based NUMA system with MINT simulator (Multiprocessor simulator)
  - Design and implement the northbridge chip (with FPGA) for Ring-based CC-NUMA system
    : The system replaces a bus with high-speed unidirectional point-to-point links
    and supports up to 64 processors for higher scalability