Changkyu Kim

Changkyu Kim

My Resume/CV || Publications || Experience || Education || Presentations || Contact Information

Research Scientist of Parallel Computing Lab, Intel Coporation
Email: changkyu.kim (at) i n t e l . c o m

Research

I am currently a research scientist at the

Parallel Computing Lab at Intel Labs, Santa Clara, CA. Before joining Intel Labs, I completed my PhD. in Computer Science from the University of Texas at Austin. I received a M.S and a B.S from Seoul National University in Computer Engineering.

Throughput Computing is a major priority for my research interest. One of my most significant research focus in this area is: analysis and synergistic combination of emerging applications including database/data-mining, massive graph processing, big data processing, exascale computing, real-time analytics, visual computing (visibility computation, physical simulation), and high-performance scientific computing with upcoming architecture trends, such as multi/many-core, reconfigurable, GPU, heterogeneous/hybrid computing.

In the past, I worked on the NUCA (Non-Uniform access Cache Architecture), the TRIPS, and the TFlex project under Dr. Doug Burger and Dr. Steve Keckler.

Publications

Full list of publications on [Google Scholar]

CloudRAMSort: Fast and Efficient Large-Scale Distributed RAM Sort on Shared-Nothing Cluster (SIGMOD 2012, coming soon!)

Closing the Ninja Performance Gap through Traditional Programming and Compiler Technology (Intel White Paper 2012)

Fast and Efficient Graph Traversal Algorithm for CPUs: Maximizing Single-Node Efficiency (IPDPS 2012, coming soon!)

Data-intensive Supercomputing: Large-Scale Graph Processing -- #6 Placement on the Graph500 Ranking -- ("Intel Press", "How are billion things related?")

Fast Updates on Read-Optimized Databases Using Multi-Core CPUs (VLDB 2012, coming soon!)

Designing Fast Architecture Sensitive Tree Search on Modern Multi-Core/Many-Core Processors (ACM TODS 2011)

PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors (VLDB 2011)

Moguls: a Model to Explore the Memory Hierarchy for Bandwidth Improvements (ISCA 2011)

Performance and Energy Implications of Many-Core Caches For Throughput Computing (IEEE Micro 2010)

3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs (SC 2010)

Debunking the 100X GPU vs. CPU Myth: An Evaluation of Throughput Computing on CPU and GPU (ISCA 2010, IMAC 2010 -- Intel Micro-Architecture Conference)

FAST: Fast Architecture Sensitive Tree Search on Modern CPUs and GPUs (ACM SIGMOD 2010) -- Best Paper Award -- ("ACM SIGMOD", "Intel Press")

Fast Sort on CPUs and GPUs: A Case For Bandwidth Oblivious SIMD Sort (ACM SIGMOD 2010)

Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs (VLDB 2009)

ClearPath: Highly Parallel Collision Avoidance for Multi-Agent Simulation (ACM SCA 2009) -- ("Movie")

Efficient shared cache management through sharing-aware replacement and streaming-aware insertion policy (IPDPS 2009)

Multitasking Workload Scheduling on Flexible-Core Chip Multiprocessors (PACT 2008)

Atomic Vector Operations on Chip Multiprocessors (ISCA 2008)

Second Life and the New Generation of Virtual Worlds (IEEE Computer 2008)

Composable Lightweight Processors (MICRO 2007)

On-Chip Interconnection Networks of the TRIPS Chip (IEEE Micro 2007)

A NUCA Substrate for Flexible CMP Cache Sharing (IEEE TPDS 2007)

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor (MICRO 2006)

Implementation and Evaluation of On-Chip Network Architectures (ICCD 2006)

A NUCA Substrate for Flexible CMP Cache Sharing (ICS 2005)

Scaling to the End of Silicon with EDGE Architectures (IEEE Computer 2004)

TRIPS: A Polymorphous Architecture for Exploiting ILP, TLP, and DLP (ACM TACO 2003)

NUCA: A Non-Uniform Cache Access Architecture for Wire-Delay Dominated On-Chip Caches (IEEE Micro Top Picks 2003)

Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture (IEEE Micro Top Picks 2003)

Exploiting ILP, DLP, and TLP Using Polymorphism in the TRIPS Architecture (ISCA 2003)

An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches (ASPLOS 2002)

Professional Activity

Program Committee in DaMoN 2010 workshop: The 6th workshop of "Data Management on New Hardware", held in conjunction with ACM SIGMOD/PODS 2010 Conference
Program Committee in MEDEA 2009 workshop: The 10th workshop of "Memory performance, Dealing with Applications, systems and architecture", held in conjunction with PACT 2009 Conference
Program Committee in MEDEA 2008 workshop: The 9th workshop of "Memory performance, Dealing with Applications, systems and architecture", held in conjunction with PACT 2008 Conference
Graduate Representative in Admissions Committee in the Department of Computer Sciences at the University of Texas at Austin (2006-2007)
Reviewer of various conferences (ISCA/MICRO/ASPLOS/HPCA/ICS/SC/IPDPS/ICCD/ISPASS/DAC) and journals (Journal of VLSI Signal Processing Systems, ACM Transactions on Architecture and Code Optimization, IEEE Transactions on VLSI Systems, Journal of Microprocessors and Microsystems, IEEE Computer Architecture Letters)