Joel Hestness
hestness <at> cs.utexas.edu
jthestness <at> gmail.com
I am currently attending the Computer Science Department of The University of Texas at Austin. I am working toward a PhD in the Computer Architecture Research and Technology Lab (CART) under Prof. Steve Keckler.
Research
My research interests include computer architecture performance and reliability. In particular, I am currently focusing on performance and reliability of on-chip networks. I am also interested in performance evaluation methodologies and power consumption/management.
I am currently using the M5 simulator, and I have built some disk images that contain PARSEC benchmark ALPHA binaries for use in M5. The current image is located here with notes on its status:
linux-parsec-golden.img.bz2
Current Image Status (README)
A script to write M5 FS run scripts is located here (note that the input sets file is required for this script to work):
Script to generate M5 FS run scripts
PARSEC command line/input set file
The first work that I did as a graduate student concerned reliability trends:
Hard Reliability Projections Spreadsheet
Reliability Costs Spreadsheet
Note: This spreadsheet contains excel macros.
About Me
I graduated from The University of Wisconsin - Madison with Bachelor's degrees in Computer Science and Mathematics.
GRACS:
I was elected as a representative of the Graduate Representation Association of Computer Science (GRACS) during my first year (2007-2008) as a graduate student.
CEO Texas:
As a member of CEO Texas, I moderated and helped organize the first ever Venture Weekend
In April 2009, we held the event under the new name, 3 Day Startup. I helped with recruitment and operations organizing for the event. We are holding the event again this fall. Check out our site, and apply now:
Publications
Express Cube Topologies for On-Chip Interconnects.
B. Grot, J. Hestness, S. W. Keckler, O. Mutlu. In 15th International Symposium on High Performance Computer Architecture (HPCA), February 2009.