Joel Hestness
hestness <at> cs.utexas.edu
jthestness <at> gmail.com
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I am currently attending the Computer Science Department of The University of Texas at Austin. I am working toward a PhD in the Computer Architecture Research and Technology Lab (CART) under Prof. Steve Keckler.
Research
My research interests include performance, power consumption and reliability of data communication in future highly-integrated chips. In particular, I have have researched on-chip networks, and I am currently researching communication and memory systems for processor chips with accelerators such as GPUs.
I am currently using the gem5 simulator, and I helped build infrastructure for running PARSEC 2.1 under gem5 ALPHA
There are disk images and scripts here: PARSEC on M5
I have developed tools and traces for enforcing dependencies between packets in trace-based network simulation.
It is called Netrace.
The first work that I did as a graduate student concerned reliability trends:
Hard Reliability Projections Spreadsheet
Reliability Costs Spreadsheet
Note: This spreadsheet contains excel macros.
Publications
Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees.
B. Grot, J. Hestness, S. W. Keckler, O. Mutlu. The 38th International Symposium on Computer Architecture (ISCA), June 2011.
FFTW and Complex Ambiguity Function Performance on the Maestro Processor.
K. Singh, J. P. Walters, J. Hestness, J. Suh, C. M. Rogers, S. P. Crago. In 32nd IEEE Aerospace Conference, March 2011.
3 Day Startup: Molding Student Entrepreneurs for Fun and Non-profit.
J. Hestness, T. Finsterbusch, C. Houser, E. Mercer, J. Guillory. In 5th International Technology, Education and Development Conference (INTED), March 2011.
Netrace: Dependency-Driven Trace-Based Network-on-Chip Simulation.
J. Hestness, B. Grot, S. W. Keckler. In 3rd International Workshop on Network on Chip Architectures (NoCArc), December 2010.
Express Cube Topologies for On-Chip Interconnects.
B. Grot, J. Hestness, S. W. Keckler, O. Mutlu. In 15th International Symposium on High Performance Computer Architecture (HPCA), February 2009.
Technical Reports
Netrace: Dependency-Tracking Traces for Efficient Network-on-Chip Experimentation.
J. Hestness, S. W. Keckler. Technical Report TR-10-11, The University of Texas at Austin, Department of Computer Science, May 2011.
Running PARSEC 2.1 on M5.
M. Gebhart, J. Hestness, E. Fatehi, P. Gratz, S. W. Keckler. Technical Report TR-09-32, The University of Texas at Austin, Department of Computer Science, Oct 2009.
About Me
I graduated from The University of Wisconsin - Madison with Bachelor's degrees in Computer Science and Mathematics.
GRACS:
I was elected as a representative of the Graduate Representation Association of Computer Science (GRACS) during my first year as a graduate student.
Student Entrepreneurship Opportunities (SEO):
As a member of SEO, I cofounded 3 Day Startup. Many 3DS alumni work at successful startups, even some started at the event. Many other universities have requested our help in organizing their own 3DS events, so we have rolled 3 Day Startup into a nonprofit. Feel free to inquire, and apply now!
