Homework Assignment 5 CS 350c Unique Number: 52140 Spring, 2017 Given: February 14, 2017 Due: February 23, 2017 This homework concerns exploring the x86 memory management mechanisms and some questions about the specificity of the x86 ISA. You may need to refer to the x86 documentation to be able to complete this assignment. In addition, this assignment asks that you carefully read Section 4.1 of "Computer Systems, A Programmer's Perspective". Your next homework assignment will involve writing a y86 ISA simulator. 1. If you want to create a set of page tables to map 21,357,113 bytes of contiguous memory, how many 4K pages would there need to be assuming that all of the memory is of the same type? 2. What is the minimum amount of memory that would be required for all of the page-table, memory-resident, mapping information necessary to make mapping possible for 21,357,113 bytes of contiguous read/write data memory when using 4K pages? 3. What is the minimum amount of memory that would be required for all of the page-table, memory-resident, mapping information necessary to make mapping possible for 21,357,113 bytes of contiguous read/write data memory when using 2M pages? 4. Does it matter where the 21,357,113 bytes start in the memory as it concerns the required number of page-table entries? 5. Using 4K pages, how large would the TLB need to be so that we could address all 21,357,113 bytes without ever needing to reload the TLB? 6. Using 2M pages, how large would the TLB need to be so that we could address all 21,357,113 bytes without ever needing to reload the TLB? Here are some questions that concern the x86 instruction-set architecture. 7. Are there x86 instructions that (potentially) produce non-repeatable answers? What do I mean? If you use the RDTSC and RDTSCP instructions to measure the duration of a program, why would you get different answers when running the same program repeatedly? Would one get a better result if one were to use a raw x86 machine; that is, a x86 system without an operating system? 8. If you write a "timing loop" program -- a program that repeats some calculation some number of times -- will it provide an accurate delay if you know the clock frequency of the processor on which you you are running your experiments? Why or why not? Explain your answer. 9. Given a simulator state like this: typedef unsigned char u8; typedef long i64; i64 rip; // y86 program counter i64 rgf[ 15 ]; // y86 registers u8 zf; // y86 zero flag u8 sf; // y86 sign flag u8 of; // y86 overflow flag u8 mem[ MEMSIZE ]; // y86 memory u8 status; // y86 processor status where MEMSIZE < 2^64, could we create a faithful simulator with respect to the y86 instruction-set architecture specification?