Jayaram
Mudigonda Lab
for Advanced Systems Research Department
of Computer Sciences jram at cs
dot utexas dot edu (512) 232 7887 (Cube) (512) 232 7886 (Fax)
My research interests lie in the intersection area of Networking, Architecture and Operating Systems.
Current state of the art in computing systems sacrifices one of the two most desirable properties, namely high performance and ease-of-programming. On the one hand, performance of the current uniprocessor systems is beginning to be limited by fundamental factors such as wire-delay. On the other hand, heterogeneous multicore architectures that can effectively circumvent such fundamental limitations are extremely hard to program.
Hence, the main theme of my research is to realize an ideal multicore computing system that can be easily programmed to achieve high performance. More precisely, my research addresses the following two important components of such an ideal system: (1) Architectural mechanisms that should be supported in order to facilitate the easy utilization of the available processor cores, and (2) Fundamental insights that enable compilers and run-time systems to automatically exercise these mechanisms and make these systems easy to program.
I began by considering packet processing systems as these systems have been at the forefront of the migration from uniprocessor to multicore systems. In my doctoral thesis, starting from first principles, I derived the design of a multicore processor for packet processing systems that, when compared to the state of the art, (1) is substantially easier to program and (2) improves the packet throughput by 300\%. My architecture achieves this by addressing the critical problem of the memory bottleneck in a fundamentally new way; it allows the fast memory within each core to be dynamically traded off between the two primary approaches to mitigating the memory access overhead: (1) reduce the average access latency by exploiting locality and (2) hide the access latency by exploiting packet-level parallelism.
Recent Publications
J. Mudigonda. Addressing the Memory Bottleneck in Packet Processing Systems. PhD thesis, Department of Computer
Sciences, University of Texas at Austin, December 2005.
J. Mudigonda, H. Vin, S. Keckler “Register Caching and Prefetching Mechanisms for Malleable Network Processors”. Under Review.
J. Mudigonda, H. Vin, R. Yavatkar. “Overcoming the memory wall in packet processing: hammers or ladders?” In ANCS ’05: Proceedings of the 2005 symposium on Architecture for networking and communications systems pages 1–10, Princeton, NJ, USA. October 2005.
J. Mudigonda, H. Vin, R. Yavatkar. “Managing Memory Access Latency in Packet Processing” In SIGMETRICS ’05: Proceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pages 396–397, Banff, Alberta, Canada. June 2005.
Awards
Intel Foundation Fellowship
MCD Fellowship, University of Texas at Austin
Merit Scholarship, REC Warangal, India
National Merit Scholarship, Government of India
10-Jan-2006