Karthikeyan Sankaralingam

CV, References
Research statement
Teaching statement
List of Publications
Select papers:
1. Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture, ISCA-30, 2003 pdf
2. Universal Mechanisms for Data-Parallel Architectures, MICRO-36, 2003 pdf
3. A Design Space Evaluation of Grid Processor Architectures, MICRO-34, 2001 pdf
Research Summary
The Grid Processor Architecture [ Paper Abstract ]
A scalable distributed microarchitecture which provides ultra-wide issue computation, large instruction windows, scales to future wire-delay dominated technologies, and can replace conventional out-of-order superscalar processors. The three main features are:
1. Encode dataflow dependences in the ISA to enable direct instruction-instruction communication and reduce the overheads of detecting and managing dependencies that conventional out-of-order processors must pay.
2. Partition the program into well-defined blocks to limit the scope of the dependencies so that the number of dependence arcs does not become too many to encode in the instruction space.
3. To manage design complexity and address wire delay scaling and reliability, the computation core is completely distributed using microarchitecture control and data networks with only nearest-neighbor links used for communication.
Polymorphous architectures - TRIPS [ Paper Abstract ]

My dissertation research introduced the concept of a polymorphous processor - one that can adapt to the workload by altering the behavior of coarse microarchitecture units to suit the application. TRIPS prototype chip ISA, microarchitecture, processor verification and physical design lead.

Mechanisms for data level parallelism [ Paper Abstract ]

In my dissertation research, I identified fundamental attributes for classifying DLP programs based on memory behavior, control structures, and amount of available parallelism. I proposed a set of universal mechanisms, which can provide architectural capability for run-time processor customization for any application sub-domain within DLP.

Ranking metrics for P2P Systems [ Paper Abstract ]

I developed a distributed formulation of the Google pagerank algorithm that can be executed on a Peer-to-Peer network. This work provides the first solution for ranking documents on P2P networks. Extending this idea to web servers I showed how to build a completely decentralized search engine.

TRIPS Prototype Processor [ Paper Abstract ]

This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution. It details each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributed microarchitectural protocols that implement instruction fetch, execution, flush, and commit. We also describe the physical design issues that arose when implementing the microarchitecture in a 170M transistor, 130nm ASIC prototype chip.
List of Publications
Patents

Research - Karthikeyan Sankaralingam