Implementing EDA Algorithms using the Operator Formulation

 

Project contacts: Yi-Shan Lu

Project description: Electronic Design Automation (EDA) tools are used for designing circuits such as FPGAs. Many EDA algorithms work with graphs, where nodes represent logic gates and directed edges signals in between logic gates. For example, to map a combinational circuit to look-up tables (LUTs) on an FPGA, one would decompose the circuit to disjoint parts in various ways, and then decide the mapping based on cost functions like delay, area, power consumption, etc.

Given a circuit, sequential algorithms described in the paper by Mishchenko et al. compute for each node “k-input cuts,” and then map sets of nodes to LUTs according to delay and area. To avoid exhaustive enumeration, they also described ways to keep only effective k-cuts.

The goal of this project is to implement the algorithms for mapping a combinational circuit to LUTs on an FPGA using Galois, a C++ library for parallel graph algorithms developed by our group. The input graphs, and-inverter graphs (AIGs), will be given to you. Though Mishchenko et al. used k-cut algorithms, you can use different algorithms. Choosing the algorithms will require thinking about what kind of costs you want to optimize, and how the algorithms can be parallelized.

Project deliverables and deadlines

1.     (Nov 1) A clear statement in English of the costs you want to optimize and the algorithms for such optimizations.

2.     (Nov 8) A description of how you will parallelize these algorithms

3.     (Dec 6) An implementation in Galois for the algorithms you choose.

4.     (Dec 6) A project report, written like an ACM conference paper, that summarizes the work you did.


Papers

1.     Improvements to technology mappings for lut-based fpgas. Alan Mishchenko, Satrajit Chatterjee and Robert K. Brayton. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, volume 26, no. 2, February 2007.

2.     Kl-cuts: a new approach for logic synthesis targeting multiple output blocks. Osvaldo Martinello Jr, Felipe S. Marques, Renato P. Ribas and Andre I. Reis. Proceedings of the Conference on Design Automation and Test in Europe, 2010.