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Ph.D.
Computer Science,University
of Texas at Austin, Austin , July 2000 - present
M.S.
Computer Science,University
of Texas at Austin, Austin , May 2004
B.Tech
Electrical Engineering,
Indian Institute of Technology, Madras
(IIT-Madras), July 2000
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I am a member of the CART research group directed jointly by Doug Burger and Steve Keckler . My research interests are in high performance computer architecture subject to the constraints imposed by performance, power consumption and reliability. I was part of the TRIPS design team. Specifically, I was responsible for the specification, design, implementation, verification, timing, and area closure of the Execution Unit in the TRIPS processor. My research focuses on exploring the susceptibility
of processors to both hard and soft errors and future technologies and designing mechanisms to improve reliability in a performance,
power and area efficient manner. During the last few years I have also worked on two Summer industry internships. In the summer of
2001 I worked with Dr. Norm Jouppi on primarily adding area modeling support to CACTI culminating in the release of CACTI 3.0. Last
summer I interned at AMD and worked on memory system optimizations in their next generation processor architecture.
Learn more about the TRIPS project here.
"Distributed Microarchitectural Protocols in the TRIPS Prototype Processor," Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert McDonald, Rajagopalan Desikan, Saurabh Drolia, M.S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger, The 39th International Symposium on Microarchitecture, December 2006 (PDF)
"Scaling to the End of Silicon with EDGE Architectures," D. Burger, S.W. Keckler, K.S. McKinley, M. Dahlin, L.K. John, C. Lin, C.R. Moore, J. Burrill, R.G. McDonald, W. Yoder, and the TRIPS Team, IEEE Computer, July 2004 (PDF)
"Exploiting Microarchitectural Redundancy For Defect Tolerance," Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, and Doug Burger, The 21st International Conference on Computer Design (ICCD), October, 2003 (PDF)
"A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems," S.W. Keckler, D.C. Burger, C.R. Moore, R. Nagarajan, K. Sankaralingam, V. Agarwal, M.S. Hrishikesh, N. Ranganathan, and P. Shivakumar, 2003 International Solid-State Circuits Conference (ISSCC), February, 2003 (PDF)
"Modeling the Effect of Technology
Trends on the Soft Error Rate of Combinational Logic,"
Premkishore Shivakumar, Michael Kistler, Stephen Keckler, Doug Burger
and Lorenzo Alvisi,
International Conference on Dependable Systems and Networks (DSN), June 2002
(PDF)
"The Optimal Useful Logic Depth Per Pipeline Stage is 6-8 F04,"
M.S. Hrishikesh, Norman P. Jouppi , Keith I. Farkas , Doug Burger , Stephen W. Keckler and Premkishore Shivakumar,
The 29th Annual International Symposium on Computer Architecture, May 2002 (PDF)
"A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems," S.W. Keckler, D.C. Burger, C.R. Moore, R. Nagarajan, K. Sankaralingam, V. Agarwal, M.S. Hrishikesh, N. Ranganathan, and P. Shivakumar,
2003 International Solid-State Circuits Conference (ISSCC), February, 2003.
pdf
bib
"Fault Aware Instruction Placement for Static Architectures,"
Premkishore Shivakumar, Divya P. Gulati, Calvin Lin and Stephen W. Keckler,
1st Workshop on High Performance Computing Reliability Issues (HPCRI), Feb 2005
(PDF)
"Exploiting Microarchitectural
Redundancy for Defect Tolerance,"
Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore
and Doug Burger,
IBM Austin Center for Advanced Studies (ACAS) Conference, February, 2003.
(PDF)
"Modeling the Effect of Technology
Trends on the Soft Error Rate of Combinational Logic,"
Premkishore Shivakumar, Michael Kistler, Stephen Keckler, Doug Burger
and Lorenzo Alvisi,
IBM Austin Center for Advanced Studies (ACAS) Conference, February, 2002.
(PDF)
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"Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of
Processor Elements,"
Premkishore Shivakumar, Michael Kistler, Stephen Keckler, Doug Burger
and Lorenzo Alvisi,
UT-Austin Computer Sciences Technical Report TR-02-19, April, 2002. (PDF)
"Cacti 3.0: An Integrated Cache Timing, Power and Area Model,"
Premkishore Shivakumar and Norman P. Jouppi ,
Western Research Lab (WRL) Research Report 2001/2
(PDF)
CACTI 3.0 includes modeling support for the area and aspect ratio of
caches, caches with independently addressed banks, reduced sense-amp
power dissipation, and other improvements to CACTI 2.0.
CACTI 3.0 can be obtained by downloading its
gzip'ed tar file,
gunzip'ing it, and extracting its tar'ed files.
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Advanced Micro Devices (AMD), Sunnyvale, CA,
June-August 2006
Performance Modeling Group
Manager: Dr. Leslie Barnes
Mentor: Dr. Paul Keltcher
Worked on performance modeling and memory optimizations in the next generation processor architecture.
Western Research Lab (WRL), Compaq, Palo Alto, CA
May-August, 2001
Advisor: Dr. Norman P. Jouppi
Developed CACTI 2.0
Static Cache Access Time, Power and Area Model
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Talk given at ICCD, October 15th, 2003
Talk given at the IBM Austin Center for Advanced Studies, 4th Annual Austin CAS Conference - February 21, 2003
Internship Talk given at Compaq Western Research Lab about Cacti 3.0, August 2001
Talk given at the IBM Austin Center for Advanced Studies, 3rd Annual Austin CAS Conference - February 15, 2002
Slides of the talk given by my co-author Mike Kistler at the International Conference on Dependable Systems and Networks, June 2002
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Contact Information
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Office Address
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ACES 3SEo5F
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Mailing Address
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Department of Computer Science
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University of Texas at Austin
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Austin, TX 78712-1188
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Home Address
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4505 Duval Street Apt 240
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Austin, TX 78751
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Telephone Numbers
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512-232-7442 (Work)
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512-419-1699 (Home)
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Email
pkishore at cs.utexas.edu
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