CS 439: HW 7

Due: 7:45 AM. Fr. Oct. 26

Turn-in Instructions

1. Use the description of Problem 9.11 in B&O, pg. 849 for these 3 virtual addresses:
   1. for virtual address: 0x027c (Problem 9.11)
      A. Virtual Address format: _ _ _ _ _ _ _ _ _ _ _ _ _ _
      B. Address Translation:
         VPN: ____ TLBI: ____ TLBT: ____ TLB hit? ____ page fault? ____ PPN: ____
      C. Physical Address format: _ _ _ _ _ _ _ _ _ _ _ _ _ _
      D. Physical memory reference:
         CO: ____ CI: ___ CT: ___ cache hit? ___ cache byte? ___
   2. for virtual address: 0x03a9 (Problem 9.12)
      A. Virtual Address format: _ _ _ _ _ _ _ _ _ _ _ _ _ _
      B. Address Translation:
         VPN: ____ TLBI: ____ TLBT: ____ TLB hit? ____ page fault? ____ PPN: ____
      C. Physical Address format: _ _ _ _ _ _ _ _ _ _ _ _ _ _
      D. Physical memory reference:
         CO: ____ CI: ___ CT: ___ cache hit? ___ cache byte? ___
   3. for virtual address: 0x0040 (Problem 9.13)
      A. Virtual Address format: _ _ _ _ _ _ _ _ _ _ _ _ _ _
      B. Address Translation:
         VPN: ____ TLBI: ____ TLBT: ____ TLB hit? ____ page fault? ____ PPN: ____
      C. Physical Address format: _ _ _ _ _ _ _ _ _ _ _ _ _ _
      D. Physical memory reference:
         CO: ____ CI: ___ CT: ___ cache hit? ___ cache byte? ___
2. B&O 9.14 (start with the source code in the solution for problem 9.5).
   Be sure to print the contents of hello.txt to ensure you made the correct change.
   Note that you can easily create the hello.txt file with:

   $ echo "Hello, world!
   " > hello.txt

   Likewise you can print its content:
   

   $ cat hello.txt

   Question: What flags are needed on the mmap call to make the file change visible?
   Copy/paste your source code solution here:

3. Given a system with:
   • Page/Frame size: 8KB
   • Private L1: Physical Address tags, 1024 entry, 4-way set associative.
   • Virtual Addresses: 48 bit
   • Physical Addresses: 31 bits (fully backed).
   Suppose we have a process, P1, with 2,048 valid pages in its page table. And during its execution, P1 references all its pages.
   
   1. Is there a scenario where never more than 4 of P1's mappings would be present in the L1 at any one time?
   2. Explain.
   3. Is there a scenario where all of 8KB of the L1 cache contains P1's data?
   4. Explain.
4. Give an example where a "page coloring" OS (A&D, page 427) could be beneficial.