A Survey of Hybrid Technques for Functional Verification

J. Bhadra, M. S. Abadir, L. Wang, and S. Ray

IEEE Design & Test of Computers, volume 24(2) March-April 2007 (Special Issue on Advances in Functional Validation through Hybrid Techniques), pages 112-122. IEEE Computer Society.

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Abstract

The increasing size and complexity of industry hardware designs, along with stringent time-to-market requirements, have put a heavy burden on verification to ensure that designs are relatively bug free. A general theme successfully adopted by academia and several vendors is to apply multiple verification techniques so that they complement one another, resulting in an increase of the verification tool's overall effectiveness. Such integration must be carried out delicately and precisely so that the overall technique becomes more than merely a sum of the techniques. This article surveys the research that has taken place in this area.

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BibTex

@Article{bhadra-survey,
  author    = "J. Bhadra and M. S. Abadir and L. Wang and S. Ray",
  title     = "{A Survey of Hybrid Technqiues for Functional Verification}",
  journal   = "{IEEE Design \& Test of Computers}",
  volume    = "24",
  number    = "2",
  pages     = "112-122",
  publisher = "{IEEE Computer Society}",
  year      = "2007"
}