Madhu Saravana Sibi Govindan

Contact:
1 University Station C0500
Austin, TX 78712-0233
Email: sibi at cs dot utexas dot edu

Office: ACES 3SEo5C
Office Phone: (512) 232-7440

TA Information for CS380P: Parallel Systems (Spring 2009)

Office Hours

Tuesdays : 1.30 - 2.30 PM
Thursdays : 10.00 - 11.00 AM
Location : ENS 31NQ

Directions : The TA stations are located in ENS 31NQ. Take the elevator down to "LB" (lower basement). Exit the elevator and go to your right. Continue down the hallway. It will curve to the right. You'll come to 31NR on your left. Go through 31NR to a smaller room. That is 31NQ.

Information on Programming Assignment 1 (Pthreads)

Information on the MPI Assignment

About Me

I'm a Doctoral Candidate in the Computer Sciences Department of UT Austin. I'm a member of the CART research group co-directed by Prof. Doug Burger and Prof. Steve Keckler. My primary advisor is Steve and I'm co-advised by Doug.

Education

PhD, Computer Sciences University of Texas at Austin	August 2003 -
MS, Computer Sciences University of Texas at Austin	August 2003 - August 2006
B. E., Computer Science and Engineering College of Engineering, Guindy, Anna University, Madras	August 1998 - May 2002

PhD Research

My research interests include power-efficient microprocessor design, hardware-software interaction for power efficiency, power modeling techniques and parallel systems in general. I'm currently exploring techniques - both hardware and software - to improve power efficiency of a class of architectures called EDGE (Explicit Data Graph Execution) architectures. The TRIPS Microarchitecture and the TFlex microarchitecture are examples of EDGE architectures. I'm exploring techniques to improve power efficiency of both TRIPS and TFlex.

I was also a member of the TRIPS prototype design team. I designed and implemented the External Bus Controller module for the TRIPS chip - the module that interfaces the chip with the external world. I was also in-charge of chip-level pre-silicon verification, TRIPS motherboard bringup and post-silicon verification of the TRIPS prototype.

Publications (Copyright restrictions apply)

Composable Lightweight Processors, Changkyu Kim, Simha Sethumathavan, M.S.Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger and Steve Keckler, Micro 2007. (PDF)

Madhu Saravana Sibi Govindan, Stephen W. Keckler, Doug Burger. "End-to-End Validation of Architectural Power Models". The University of Texas at Austin, Department of Computer Sciences. Report# TR-08-37 (regular). September 2, 2008. (PDF)

TRIPS: A Distributed Explicit Data Graph Execution (EDGE) Microprocessor," M.S. Govindan, K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, P. Gratz, D. Gulati, H. Hanson, C.K. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S.W. Keckler, and D. Burger, HotChips 19, August, 2007. (PDF)

"Software Infrastructure and Tools for the TRIPS Prototype," B. Yoder, J. Burrill, R. McDonald, K. Bush, K. Coons, M. Gebhart, M.S. Govindan, B. Maher, R. Nagarajan, B. Robatmili, K. Sankaralingam, S. Sharif, A. Smith, D. Burger, S.W. Keckler, and K.S. McKinley, Workshop on Modeling, Benchmarking and Simulation (MoBS), June, 2007.

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor, The TRIPS Team, MICRO'06 (PDF)

Govindan, Madhu Saravana Sibi, Stephen W. Keckler, Sani Nassif, and Emrah Acar. "A Temperature-Aware Power Estimation Methodology". The University of Texas at Austin, Department of Computer Sciences. Report# TR-07-43 (regular tech report). August 29, 2007. (PDF )