Late changes in silicon design (ECO) is a common although undesired practice. The need for ECO exists even in high-level design flows since bugs may occur in the specifications, in the compilation, or due to late spec changes. Esterel compilation deploys sequential optimization to improve delay and area of the netlist. This makes harder to find in the netlist where manual changes should be done and to trace circuit changes back to the high-level spec. We show that all sequential optimizations used in Esterel compilation can be made reversible and demonstrate that an ECO problem can be reduced to a commonly solved combinational ECO problem by reconstructing some of the suppressed registers in order to backannotate to the original code. We demonstrate that the cost of reversibility is neglegible.