• Top
  • Documentation
  • Books
  • Recursion-and-induction
  • Boolean-reasoning
  • Debugging
  • Projects
  • Std
  • Proof-automation
  • Macro-libraries
  • ACL2
  • Interfacing-tools
  • Hardware-verification
    • Gl
    • Esim
      • Symbolic-test-vectors
        • Defstv
        • Stv-compile
        • Symbolic-test-vector-format
        • Stv-implementation-details
        • Compiled-stv-p
          • Compiled-stv
          • Make-compiled-stv
          • Change-compiled-stv
          • Honsed-compiled-stv
          • Make-honsed-compiled-stv
          • Compiled-stv->restrict-alist
          • Compiled-stv->override-paths
          • Compiled-stv->override-bits
          • Compiled-stv->out-usersyms
          • Compiled-stv->out-extract-alists
          • Compiled-stv->nst-extract-alists
          • Compiled-stv->nphases
          • Compiled-stv->int-extract-alists
          • Compiled-stv->in-usersyms
          • Compiled-stv->expanded-ins
        • Stv-run-for-all-dontcares
        • Stv-run
        • Stv-process
        • Stv-run-check-dontcares
        • Symbolic-test-vector-composition
        • Stv-expand
        • Stv-easy-bindings
        • Stv-debug
        • Stv-run-squash-dontcares
        • Stvdata-p
        • Stv-doc
        • Stv2c
        • Stv-widen
        • Stv-out->width
        • Stv-in->width
        • Stv->outs
        • Stv-number-of-phases
        • Stv->ins
        • Stv-suffix-signals
        • Stv->vars
      • Esim-primitives
      • E-conversion
      • Esim-steps
      • Patterns
      • Mod-internal-paths
      • Defmodules
      • Esim-simplify-update-fns
      • Esim-tutorial
      • Esim-vl
    • Vl2014
    • Sv
    • Fgl
    • Vl
    • X86isa
    • Svl
    • Rtl
  • Software-verification
  • Testing-utilities
  • Math

• Compiled-stv-p

Compiled-stv->in-usersyms

Access the in-usersyms field of a compiled-stv-p structure.