The VL Verilog Toolkit is a large ACL2 library for working with SystemVerilog (and also
regular Verilog) source
code, developed at Centaur Technology by Jared Davis and Sol Swords. It serves
as a frontend for many Verilog tools.
ALPHA VERSION. The new
development version of VL is not yet ready for public use and may change in
drastic ways without any warning. Users who want to be on the bleeding edge
should follow the github project to try to keep up to date. Alternately, see
vl2014 for a more stable (but less fully featured) version of
Note: this documentation is mainly a reference manual.
If you are new to VL, please see getting-started first.
- Internal representation of the syntax of Verilog and SystemVerilog.
- Finds and loads Verilog or SystemVerilog source files—generally
the first step toward using VL to work with a hardware design.
- Support for handling warnings and errors.
- An introduction to VL, with suggested starting points for how to get
started with evaluating it for use in your own projects.
- Generic utilities that are unrelated to Verilog processing, but which
are provided by the VL books.
- The VL printer is a tool for building strings. It is generally used
to pretty-print our internal Verilog syntax back out into text or HTML.
This is very useful in warnings, the vl-server, and other
- A command-line program for using vl in basic ways.
- Module Library -- A collection of various functions for
working with Verilog modules.
- High-level transformations for rewriting and simplifying Verilog