Welcome to VWSIM tutorial! We will go through simulating various circuits to get familiar with the simulator and its many options.
VWSIM provides simulation capabilities for hierarchical circuit models. These models specify VWSIM primitives (resistors, capacitors, inductors, Josephson junctions, transmission lines, transformers, and current, voltage, and phase sources) and how they are connected.
VWSIM accepts input models for simulation in two, text-based formats: the SPICE format and the VWSIM native format. VWSIM does not provide CAD or schematic capture capabilities; we do not discuss options for using a CAD system to provide a means to create SPICE or VWSIM compatible input (models). However, we note that our typical process involves creating a schematic using the GNU Electric CAD tool, and then asking that tool to produce a SPICE-compatible netlist that VWSIM can process. Even though VWSIM can read SPICE formatted input, VWSIM supports a small number of input components compared to a typical SPICE-compatible simulator (see vwsim-spice). VWSIM has been designed with a focus on RSFQ circuit models.
To prepare input for VWSIM, one may use an editor (or some other process) to produce a netlist that can be read by VWSIM in vwsim-spice or vwsim-hdl format. Such a hierarchical netlist identifies all primitive devices and also describes the connection between all primitive devices. To cause VWSIM to animate such a netlist, a user also must provide time-varying voltage, current, and phase sources so that the model to be simulated will attempt to respond to these sources. All primitives (components and sources) are combined and simplified into a single, flat netlist composed of only primitives connected (by references) to other primitives. After a simulation, we observe time-varying changes to the model in terms of voltages, currents, and phases -- generally, by graphing them using a plotting program, such as GNUPlot. In some cases, we write ACL2 code to perform post-processing of the simulation values that were saved during a simulation.
Given an acceptable model, meaning that each primitive component is connected to other primitive components, VWSIM attempts to build an internal model vwsim to be simulated. If a model can be constructed, then VWSIM will attempt to simulate the accepted model -- saving intermediate voltage, current, and phase values for subsequent processing.
In our VWSIM use tutorials, we provide several example (circuit) models, and we indicate what commands a user evaluates in the ACL2 Read-Eval-Print Loop (REPL) to cause VWSIM to do its work.
Start: Simulating a simple circuit