Primitive E module for a Verilog === operator.
We use this to implement vl2014::*vl-1-bit-ceq*.
However, the === operator is inherently unsound and cannot be modeled
in esim because it is violates 4v-monotonicity. We just conservatively
approximate === with an xnor gate. That is, this module is nothing more
than a *esim-xnor*.
:x (:out ((|out| iff |a| |b|)))
:i ((|a|) (|b|))