Introduce VL_DESIGN_WIRE annotations that say which wires/regs
were in the original Verilog modules.
This transform is ordinarily run very early in the transformation
sequence by annotate. We simply extend every variable declaration with
a VL_DESIGN_WIRE attribute. This
attribute can later be used to distinguish between:
- wires that are really present and visible in the design, and
- wires that VL added in transforms like split and occform.
That is, when temporary wires are added to the module by subsequent VL
transforms, they will not have this attribute. Hence, you can check for this
attribute to tell whether a variable was in the original design.
- (vl-vardecllist-designwires x) maps vl-vardecl-designwires across a list.
- (vl-modulelist-designwires x) maps vl-module-designwires across a list.
- Add a VL_DESIGN_WIRE attribute to a vl-vardecl-p.
- Add a VL_DESIGN_WIRE attribute to every net and reg declaration
in a module.