Generation of new primitives for edge-triggered always
See edgesynth for an overview of how we handle edge-triggered
To support these blocks, VL creates primitive flip-flop modules with some
number of edges. For instance, the primitive 3-edge flop can be described as
follows in Verilog, and could be used to implement a flip-flop with, e.g.,
asynchronous set and reset signals.
module VL_1_BIT_3_EDGE_FLOP (q, d0, d1, d2, clk0, clk1, clk2);
output reg q;
input d0, d1, d2;
input clk0, clk1, clk2;
always @(posedge clk0 or posedge clk1)
q <= d0
else if (clk1)
q <= d1;
q <= d2;
The functions below generate these primitive modules and their corresponding
- (vl-make-same-bitselect-from-each x index) maps vl-make-bitselect across a list.
- Helper function for creating lists of primitive port declarations.
- Build the Verilog if-statement for a primitive n-edge flop.
- Build the primitive VL module for an n-edge flop.
- Build the Verilog always statement for a primitive n-edge flop.
- Build a 4v-sexpr with the update function upon a posedge.
- Build the Verilog sensitivity list for a primitive n-edge flop.
- Build a 4v-sexpr that captures when any clock has just had a posedge.