A parser for a subset of Verilog and SystemVerilog.
Our parser is responsible for processing a list of tokens into our internal representation of Verilog syntax. Typically these tokens are produced by the lexer. Note that before parsing begins, any whitespace or comment tokens should be removed from the token list; see for instance vl-kill-whitespace-and-comments.
We use essentially a manual recursive-descent style parser. Having the entire token stream available gives us arbitrary lookahead, and we occasionally make use of backtracking.
Verilog and SystemVerilog are huge languages, and we can parse only a subset of these languages.
We can currently support most of the constructs in the Verilog 1364-2005 standard. Notably, we do not yet support user-defined primitives, generate statements, specify blocks, specparams, and genvars. In some cases, the parser will just skip over unrecognized constructs (adding warnings when it does so.) Depending on what you are doing, this behavior may be actually appropriate, e.g., skipping specify blocks may be okay if you aren't trying to deal with low-level timing issues.
We are beginning to work toward supporting SystemVerilog based on the 1800-2012 standard. But this is preliminary work and you should not yet expect VL to correctly handle any interesting fragment of SystemVerilog.