Subtle notes about or
There are many subtleties related to
BOZO most of my testing was done on Verilog-XL before I really knew much about NCVerilog. It would be good to double-check all of these things on NCVerilog and make sure it behaves the same.
An important thing to realize is that the text which follows "
`define foo 3 `define bar `foo `undef foo `define foo 4
the value of `bar will be 4.
On both Verilog-XL and NCVerilog, it appears that an
Then we can do things like this:
`define foo `ifdef foo `include "endif.v" // the `ifdef has now ended
// suppose bar is undefined `ifdef bar `include "endif.v" // the `ifdef has not ended yet, so the include is not expanded `endif
We think this is pretty reasonable so we mimic this behavior.
`define condition 1 `define myendif `endif `ifdef condition assign w1 = 1 ; `myendif
Another subtlety. As expected, defines found within ifdefed-away parts of the code have no effect. For example, if not_defined is not defined, then upon running
`define foo 3 `ifdef not_defined `define foo 4 `endif
the value of
`ifdef not_defined `define myendif `endif `endif
This is insane, so we prohibit things like
We do not allow compiler directive names to be
Note that macro names can be simple or escaped identifiers. In Section
3.7.1, we are told that the leading backslash character and trailing whitespace
are not considered part of an escaped identifier, and that the escaped
`define foo 3 `define \bar 4 assign w1 = `foo ; assign w2 = `\foo ; assign w3 = `bar ; assign w4 = '\bar ;
In Section 19.3.1, we are told that all compiler directives shall be considered predefined macro names, and it shall be illegal to redefine a compiler directive as a macro name. And Verilog-XL seems to rightfully complain about things like:
`define define 5 `define ifdef 6
And yet, Verilog-XL permits the following:
`define \define 5 `define \ifdef 6 assign w1 = `\define ; assign w2 = `\ifdef ;
While the following will be errors:
assign w3 = `define ; assign w4 = `ifdef ;
always evaluate to true? But in Verilog-XL this is false unless you have
At any rate, to entirely avoid the question of what the right behavior is
here, we simply prohibit the use of compiler directives, whether escaped or
not, as names anywhere in
From 19.3.1, the macro text for a define is:
On the surface, this is straightforward enough. But it is difficult to know exactly how comments and these line continuations are supposed to interact. And Verilog-XL, in particular, has some very strange and seemingly inconsistent rules:
`define foo 5 // comment (accepted) 'h4 `define foo 5 // comment \ (rejected) 'h4 `define foo 5 \/* comment */ (rejected) 'h4 `define foo 5 /* comment \ (accepted) */ 'h4 `define foo 5 /* comment (rejected) */ 'h4
To prevent any amiguity, we prohibit any combination of comments and continuations that seems difficult to understand. In particular, we impose the following "cowardly" restrictions on macro text:
These constriants make reading until the end of the macro text fairly complicated since we cannot stupidly read the text without interpreting it; rather we have to look for string literals, comments, escaped identifiers, etc. The goal is for everything we support will be interpreted in the same way by Verilog-XL and other tools.