Subtle notes about
The Verilog spec is very vague about how
It does nicely explain that we are to simply replace the
The spec explicitly says the filename can be an absolute or relative pathname. In the case of an absolute pathname, the intention seems pretty clear.
Unfortunately, the spec does not explain anything about what a relative path is relative to. Upon reading the spec, I thought, "well, obviously it means relative to whatever file is currently being processed." But it turns out that this is not at all how Verilog-XL and NCVerilog handle things.
Instead, both of these tools include a notion of include directories. These directories are similar to, but distinct from, the library directories which are used to load "missing" modules. These directories are configured with command-line options like:
+incdir+/home/jared/dir1 +incdir+/home/jared/dir2 ...
When these tools see
Because of this, it does not work to just try to write includes relative to whatever file is being loaded, you just always write them relative to whatever the include path is going to be.