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Identify modules in our supported subset of Verilog.
We say a module is reasonable if it
Even though our parser essentially establishes that the files we have just read are syntactically well-formed, this does not necessarily mean the files are semantically well-formed. For instance, a module might illegally declare the same wire twice, or perhaps we have tried to declare two modules with the same name. So, our reasonableness check is important for ensuring the basic semantic correctness of the modules we are examining.
We also regard many perfectly valid Verilog constructs as unreasonable, for the simple pragmatic reason that we are only really interested in dealing with the small subset of Verilog that we actually encounter at Centaur. There is little motivation for us to support things like complicated port lists merely because they are in the Verilog-2005 standard.