High-level transformations for rewriting and simplifying Verilog
- Calculate the widths and types of expressions.
- Transform assignments into occurrences.
- Rewrite expressions to eliminate various operators.
- Expand away function declarations and calls.
- Convert delays into explicit module instances.
- Expand away modules with parameters; similar to the idea of
elaboration of the design.
- Replace vl-casestmts with equivalent vl-ifstmts.
- Split up expressions by generating new wires.
- Simplification of select expressions, e.g., mywire[3-1].
- Replace integer literals with X and Z values with concatenations of
- A set of changes to be made to a module.
- Eliminate arrays of gate and module instances.
- Simplification of ranges, e.g., reg [6-1:0]
- Eliminate assignments to simple "intermediate" wires. (UNSOUND)
- Simplify concatenations and selects throughout a module.
- Eliminate unused parameters from modules.
- A transformation which "fills in" blank arguments.
- A transform for inlining basic modules.
- Carry out basic expression simplification. (UNSOUND)
- Eliminate implicit truncations in assignments
- Transforms for synthesizing always blocks.
- Split up gates with "extra" terminals.
- Convert gate instances into instances of VL primitives.
- Simplify expressions in a few trivial ways, mainly to clean up ugly
- Elimination of supply0 and supply1 wires
- Elimination of wildcard equality operators, ==? and !=?.
- Eliminate "blank ports" from modules and delete all corresponding
arguments from module instances.
- A transform to clean up all the warnings in a design.
- Name any unnamed gate or module instances
- Ways of extending vl-simplify with custom transformations.
- A first step in most transformation sequences. Applies several
basic, preliminary transforms to normalize the original design.
- Simple pattern matching for recognizing latches.
- Remove any variable declarations that are never used.
- Eliminate modules (that the user) says cause problems.