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Vl2014

Use-set

Tool for detecting unused and unset wires.

USE-SET is a simple tool for detecting wires which may be unset or unused. This is a primitive, static analysis that can be carried out on the Verilog source tree.

Unset wires are those which have no values flowing into them. An unset wire should satisfy the following properties:

No "assign" statement is assigning a value to it, and
It is not in any submodule's output ("driven from below")
It is not a primary input ("driven from above")

Unused wires are those whose values are not sent anywhere. An unused wire should satisfy the following properties:

It is not in the RHS of any assignment
It is not in any submodule's input ("possibly used below")
It is not a primary output ("possibly used above")

Limitations

USE-SET does not currently look at always or initial statements. If wires are only used or set in these statements, they may not be reported correctly.
USE-SET is not at all clever: it will not realize that bar is unused in code such as assign foo = 1'b0 & bar; or assign foo = {0 {bar}};
USE-SET does not know about the C code that implements RAM modules in speedsim, etc., and will think that such wires are unset.
USE-SET does not consider the individual bits of a vector. For instance, if you just write:
```
wire [7:0] foo;
assign foo[0] = 1'b0;
```
It treats the entire wire foo as set, even though foo[0] is the only bit that has really been set.

Implementation

To carry out the analysis, our high-level approach is as follows. For each module, we construct a fast alist that associates each wire with a VL-WIREINFO object. This info object includes boolean flags that indicate whether the wire has been used or set. Then, we simply walk over this alist to print out any wires which are either unused or unset. We imagine that we may eventually want to add additional kinds of information here.

Subtopics

Typo-detection: We try to detect possible typos in wire names.
Vl-wireinfo-alistp: (vl-wireinfo-alistp x) recognizes association lists where every key satisfies stringp and each value satisfies vl-wireinfo-p.
Vl-annotate-vardecllist-with-wireinfo: (vl-annotate-vardecllist-with-wireinfo x alist wwires) maps vl-annotate-vardecl-with-wireinfo across a list.
Vl-useset-report-entry-p: An object that concisely captures our use-set analysis for each module; it is relatively easy to print this object as a report.
Vl-print-useset-report-entry: Print an individual entry in the use-set report.
Vl-mark-wires-for-module: Main function that performs the use-set analysis. We figure out which wires appear to be used and unused in the module X. We annotate the vardecls for the module with these attributes, and also generate a more concise vl-useset-report-entry object describing the status of this module.
Vl-split-useset-report: Filter modules based on which of them have use-set problems.
Vl-mark-wires-for-modinst
Vl-mark-wires-for-gateinstlist
Vl-annotate-vardecl-with-wireinfo: Annotate vardecls with the results of use-set analysis.
Vl-mark-wires-for-modinstlist
Vl-mark-wires-for-gateinst
Vl-mark-wires-for-plainarg: Process a plain argument and mark its wires in the alist. If the direction of the argument hasn't been resolved, return the list of any wires that have been used, so that we can issue a warning about them.
Vl-wireinfo-p: Information about a single wire.
Vl-mark-wires-for-modulelist: Carry out use-set analysis on all modules.
Vl-vardecllist-impexp-names: Split a list of net declarations into those which are implicit and those which are explicit. Note that this only works if vl-modulelist-make-implicit-wires has been run!
Vl-report-totals
Vl-mark-wires-for-plainarglist
Vl-collect-unused-or-unset-wires: Gather names of unused/unset wires from a wireinfo alist.
Vl-clean-up-warning-wires: Remove any warning wires that we know are used and set.
Vl-useset-report-p: (vl-useset-report-p x) recognizes lists where every element satisfies vl-useset-report-entry-p.
Vl-print-useset-report-top
Vl-mark-wires-for-arguments
Vl-star-names-of-warning-wires: Change names in x by putting a * in front of any name that is among the warning-wires.
Vl-design-use-set-report
Vl-module-impexp-names
Vl-make-initial-wireinfo-alist: Create an initial wireinfo alist by we associating each wire with a new vl-wireinfo entry.
Vl-mark-wires-for-assignment
Vl-mark-wires-for-assignlist
Vl-mark-wire-used
Vl-mark-wire-set
Vl-mark-wires-used
Vl-mark-wires-set
Vl-print-useset-report-full-aux
Vl-print-typo-alist
Vl-print-typo-possibilities