Tool for detecting unused and unset wires.
USE-SET is a simple tool for detecting wires which may be unset or unused. This is a primitive, static analysis that can be carried out on the Verilog source tree.
Unset wires are those which have no values flowing into them. An unset wire should satisfy the following properties:
Unused wires are those whose values are not sent anywhere. An unused wire should satisfy the following properties:
wire [7:0] foo; assign foo = 1'b0;It treats the entire wire
To carry out the analysis, our high-level approach is as follows. For each module, we construct a fast alist that associates each wire with a VL-WIREINFO object. This info object includes boolean flags that indicate whether the wire has been used or set. Then, we simply walk over this alist to print out any wires which are either unused or unset. We imagine that we may eventually want to add additional kinds of information here.