Primitive assignment module.
The Verilog definition of this module is:
module VL_1_BIT_ASSIGN (out, in) ; output out; input in; assign out = in; endmodule
VL takes this as a primitive. This module is also the basis for wider assignment modules; see vl-make-n-bit-assign.
Something subtle is that there is probably no way to implement
Originally our occform transformation tried to use buffers for assignments since this seemed to be more conservative. But these extra buffers seemed to often be inappropriate, especially when dealing with lower level modules that involve transistors.
(defconst *vl-1-bit-assign* (b* ((name "VL_1_BIT_ASSIGN") (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF"))) ((mv out-expr out-port out-portdecl out-vardecl) (vl-primitive-mkport "out" :vl-output)) ((mv in-expr in-port in-portdecl in-vardecl) (vl-primitive-mkport "in" :vl-input)) (assign (make-vl-assign :lvalue out-expr :expr in-expr :loc *vl-fakeloc*))) (hons-copy (make-vl-module :name name :origname name :ports (list out-port in-port) :portdecls (list out-portdecl in-portdecl) :vardecls (list out-vardecl in-vardecl) :assigns (list assign) :minloc *vl-fakeloc* :maxloc *vl-fakeloc* :atts atts :esim acl2::*esim-id*))))