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• Primitives

*vl-1-bit-ground*

Primitive ground or supply0 signal.

The Verilog definition of this module is:

module VL_1_BIT_GROUND (out) ;
  output out;
  supply0 out;
endmodule

VL takes this as a primitive. This module is typically introduced by the elim-supplies transform to replace supply0 wires.

The corresponding esim primitive is ACL2::*esim-f*. This is also how esim treats *vl-1-bit-f*, i.e., in esim there is no difference between ground and an ordinary constant 1'b0 value. We have a separate primitive mainly so that other backends with more transistor-level support can implement them in other ways.

Definition: *vl-1-bit-ground*

(defconst *vl-1-bit-ground*
  (b* ((name "VL_1_BIT_GROUND")
       (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
       ((mv ?out-expr
            out-port out-portdecl out-vardecl)
        (vl-primitive-mkport "out" :vl-output))
       (nettype :vl-supply0)
       (out-portdecl (change-vl-portdecl out-portdecl
                                         :nettype nettype))
       (out-vardecl (change-vl-vardecl out-vardecl
                                       :nettype nettype)))
    (hons-copy (make-vl-module :name name
                               :origname name
                               :ports (list out-port)
                               :portdecls (list out-portdecl)
                               :vardecls (list out-vardecl)
                               :minloc *vl-fakeloc*
                               :maxloc *vl-fakeloc*
                               :atts atts
                               :esim acl2::*esim-f*))))