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• Primitives

*vl-1-bit-pullup*

Primitive pullup element.

The Verilog meaning of this module is:

module VL_1_BIT_PULLUP (a, b, ctrl);
  output out;
  pullup gate (out);
endmodule

VL takes this as a primitive. The gate-elim transform converts certain pullup gates into instances of this module.

There is no sensible way to model this in ESIM and hence there is no ESIM equivalent. However, this module may be a convenient target for other back-end tools.

Definition: *vl-1-bit-pullup*

(defconst *vl-1-bit-pullup*
  (b* ((name "VL_1_BIT_PULLUP")
       (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
       ((mv out-expr
            out-port out-portdecl out-vardecl)
        (vl-primitive-mkport "out" :vl-output))
       (gate (make-vl-gateinst
                  :type :vl-pullup
                  :name "gate"
                  :args (list (make-vl-plainarg :expr out-expr
                                                :dir :vl-output))
                  :loc *vl-fakeloc*)))
    (hons-copy (make-vl-module :name name
                               :origname name
                               :ports (list out-port)
                               :portdecls (list out-portdecl)
                               :vardecls (list out-vardecl)
                               :gateinsts (list gate)
                               :minloc *vl-fakeloc*
                               :maxloc *vl-fakeloc*
                               :atts atts
                               :esim nil))))