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• Primitives

*vl-1-bit-rtranif1*

Primitive, resistive, conditional bidirectional connection.

The Verilog meaning of this module is:

module VL_1_BIT_RTRANIF1 (a, b, ctrl);
  inout a ;
  inout b ;
  input ctrl ;
  rtranif1 gate (a, b, ctrl) ;
endmodule

VL takes this as a primitive. The gate-elim transform converts certain rtranif1 gates into instances of this module.

There is no sensible way to model this in ESIM and hence there is no ESIM equivalent. However, this module may be a convenient target for other back-end tools.

Definition: *vl-1-bit-rtranif1*

(defconst *vl-1-bit-rtranif1*
 (b*
  ((name "VL_1_BIT_RTRANIF1")
   (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
   ((mv a-expr a-port a-portdecl a-vardecl)
    (vl-primitive-mkport "a" :vl-inout))
   ((mv b-expr b-port b-portdecl b-vardecl)
    (vl-primitive-mkport "b" :vl-inout))
   ((mv ctrl-expr
        ctrl-port ctrl-portdecl ctrl-vardecl)
    (vl-primitive-mkport "ctrl" :vl-input))
   (gate
    (make-vl-gateinst :type :vl-rtranif1
                      :name "gate"
                      :args (list (make-vl-plainarg :expr a-expr
                                                    :dir :vl-inout)
                                  (make-vl-plainarg :expr b-expr
                                                    :dir :vl-inout)
                                  (make-vl-plainarg :expr ctrl-expr
                                                    :dir :vl-input))
                      :loc *vl-fakeloc*)))
  (hons-copy
       (make-vl-module
            :name name
            :origname name
            :ports (list a-port b-port ctrl-port)
            :portdecls (list a-portdecl b-portdecl ctrl-portdecl)
            :vardecls (list a-vardecl b-vardecl ctrl-vardecl)
            :gateinsts (list gate)
            :minloc *vl-fakeloc*
            :maxloc *vl-fakeloc*
            :atts atts
            :esim nil))))