Typically the first step after loading a design. Applies several basic, preliminary transforms
to normalize the design and check it for well-formedness.
The vl-designs produced by VL's loader are not yet in
a very finished or error-checked form. The function vl-annotate-design
transforms such a ``raw'' design into something that is much more reasonable to
work with. Typically it should be invoked immediately after loading as the
first step in any VL-based tool.
- Split increment, decrement, and assignment operators out of
expressions and into separate statements.
- Create explicit declarations for implicit wires. This is generally
the first step after parsing a design.
- Handling of basic SystemVerilog bind constructs.
- Converts named argument lists into plain argument lists, and
annotates each plain argument with its direction.
- Basic sanity checking of various constructs.
- Fix up type (signedness) information between port and variable
- Making sense of the names defined by enum types.
- Tricky post-parsing code to get all the ports straightened out.
- Eliminate user-defined primitives (UDPs), replacing them with
- Top level annotate transform.