Handling of string literals.
String literals are sequences of ASCII characters that are enclosed in "double quotes."
Verilog-2005 and SystemVerilog-2012 have some differences here, and Verilog implementations like Verilog-XL, NCVerilog, and VCS generally don't seem to follow the standard. We discuss some of the nuances here.
The Verilog-2005 standard says that strings are contained on a single line,
but SystemVerilog-2012 adds a line continuation sequence,
$display("Hello \ World");
Is invalid in Verilog-2005, but prints
What counts as a newline? Let
We will allow or prohibit line continuations based on the vl-edition-p being used. When it is allowed, we will accept only exactly
Verilog-2005 (Section 3.6.3) could be interpreted as prohibiting raw tab characters, but experimentation with tools like Verilog-XL, NCVerilog, and VCS suggest that tab characters should be accepted in strings, so we allow them.
Strings in both Verilog-2005 and SystemVerilog-2012 can make use of the following, basic escape sequences:
These sequences seem to work on Verilog-XL, NCVerilog, and VCS without any issues.
Verilog-2005 also allows for the encoding of arbitrary ASCII characters using an octal escape sequences.
| Character by octal code of 1-3 digits
Note that 377 in octal is 255 in decimal, so a sequence such as
The Verilog-2005 standard explains the handling of
In the SystemVerilog standard, they have replaced the informal description
of octal digits with the more precise
This means that certain sequences like
In practice, none of Verilog-XL, NCVerilog, or VCS implements this restriction. However, since these are probably a very rare and esoteric thing to write in the first place, it seems reasonable for VL to prohibit these sequences.
The SystemVerilog-2012 standard introduces some new, simple escape sequences:
None of these sequences seem to be implemented on Verilog-XL, NCVerilog, or
VCS. Instead, when these tools encounter sequences like
We nevertheless try to follow the standard, and properly implement these escape sequences for suitable vl-edition-ps.
SystemVerilog 2012 also adds some ambiguous language (Section 5.9) that Nonprinting and other special characters are preceded with a backslash. It's not clear whether this is just an informal description of what the escape tables mean, or if we're supposed to allow any non-printable character to be included in a string literal by preceding it with a backslash. But it appears (cosims/str) that other tools allow most characters to be preceded by a backslash in which case they expand to themselves. We try to be compatible where we think this seems safe.
SystemVerilog-2012 also adds a way to specify characters by hexadecimal character codes:
|Character by one or two hex digits
As with octal digits, the definition is muddled by the use of
None of Verilog-XL, SystemVerilog, or VCS seems to implement hex escapes
yet. Instead, sequences like