Basic check for declaration-time assignments to logic variables.
SystemVerilog encourages logic designers to use logic
variables to avoid having to distinguish between nets and regs. But a
fundamental problem with this is that declaration-time assignments to regs and
nets are very different. For instance,
wire [3:0] foo1 = a + b; // Continuous assignment to foo1
reg [3:0] foo2 = a + b; // One-time, initial assignment to foo2
Since logic variables act like regs here, a logic designer who
logic [3:0] foo3 = a + b;
gets a one-time, initial value assignment to foo3, which is quite
possibly not at all what they meant if they've been led to believe that
logic is a new, wonderful replacement for both wire or reg.
Here we just implement a completely stupid check to look for
declaration-time assignments of variables. If we see an assignment to a
reg variable we don't complain, but if we see an assignment to something
else we issue a warning.
- (vl-modulelist-logicassign x) maps vl-module-logicassign across a list.