Checks to ensure that expressions used in lvalue positions are valid in the sense of vl-expr-net-lvalue-p or vl-expr-variable-lvalue-p, depending on the context.
Throughout our representation of Verilog/SystemVerilog syntax, we just use ordinary expressions to represent lvalues. In many cases our parser is more restrictive than this suggests. For instance, the parser will not accept syntax such as
assign a + b = c;
However, there are other places where a proper lvalue probably ought to be expected that we may not understand at parse time. For instance, the arguments to the output ports of a module instance probably ought to be good lvalues. That is, if you have:
module myadder(output [3:0] out, input [3:0] a, input [3:0] b);
Then you should probably never try to write something like:
myadder adder1 (a + b, foo, bar);
Because then you're trying to connect the adder's output to
So, in this simple vl-lint check we simply walk over the design and look for places where it seems like non-lvalues are being used where lvalues are probably expected. This is purely heuristic so the warnings we generate are never fatal.
We assume that at least argresolve has been run.