Check for odd expressions that might indicate precedence problems.
This is some rough code for finding expressions that might have
Consider the expression a & b < c. Due to the Verilog precedence
rules, this gets parsed as a & (b < c). Well, that might be quite
surprising. We try to look for expressions like this and, unless the code
contains explicit parens around the (b < c) part, we issue a warning that
it might not have the expected precedence.