High-level transformations for rewriting and simplifying Verilog
- Expand away modules with parameters; similar to the idea of
elaboration of the design.
- Resolve constant expressions, parameter values, and datatypes.
- Name any unnamed gate instances, block statements, generates, etc.
- Typically the first step after loading a design. Applies several basic, preliminary transforms
to normalize the design and check it for well-formedness.
- A transform to clean up all the warnings in a design.
- Throw away any initial statements and add non-fatal warnings to the affected modules.
- Ways of extending VL with custom transformations.
- Eliminate modules that (the user says) cause problems.