Representation of an always statement.
This is a product type introduced by defprod.
- type — vl-alwaystype-p
- What kind of always block this is, e.g., always, always_comb,
always_latch, or always_ff.
- stmt — vl-stmt
- The actual statement, e.g., @(posedge clk) myreg <= in
below. The statement does not have to include a timing control like
@(posedge clk) or @(a or b or c), but often does.
- atts — vl-atts
- Any attributes associated with this always block.
- loc — vl-location
- Where the always block was found in the source code.
Always statements in Verilog are often used to model latches and
flops, and to set up other simulation events. A simple example would be:
module mymod (a, b, ...) ;
always @(posedge clk) myreg <= in;
- Recognizer for vl-always structures.
- Fixing function for vl-always structures.
- Basic equivalence relation for vl-always structures.
- Basic constructor macro for vl-always structures.
- Get the type field from a vl-always.
- Modifying constructor for vl-always structures.
- Get the stmt field from a vl-always.
- Get the loc field from a vl-always.
- Get the atts field from a vl-always.