Representation of a continuous assignment statement.
This is a product type introduced by defprod.
- lvalue — vl-expr
- The location being assigned to.
- expr — vl-expr
- The right-hand side.
- loc — vl-location
- Where the assignment was found in the source code.
- atts — vl-atts
- Any attributes associated with this assignment.
- strength — vl-maybe-gatestrength
- delay — vl-maybe-gatedelay
In the Verilog sources, continuous assignment statements can take
two forms, as illustrated below.
module m (a, b, c) ;
wire w1 = a & b ; // <-- continuous assignment in a declaration
assign w2 = w1; // <-- continuous assignment
Regardless of which form is used, the parser generates a
vl-assign-p object. Note that the following is also legal Verilog:
assign foo = 1, bar = 2;
But in such cases, the parser will create two vl-assign-p objects, one
to represent the assignment to foo, and the other to represent the
assignment to bar. Hence, each vl-assign-p represents only a single
The lvalue field must be an expression, and represents the location
being assigned to. The formal syntax definition for Verilog only permits
lvalues to be:
- bit- or part-selects, and
- concatenations of the above.
Furthermore, from Table 6.1, (p. 68), we find that only net
declarations are permitted in continuous assignments; regs, integers,
and other variables must be assigned only using procedural assignments. We
have experimentally verified (see test-assign.v) that Cadence enforces
Our parser does impose these syntactic restrictions, but in vl-assign-p
we are perhaps overly permissive, and we only require that the lvalue is
an expression. Even so, some transforms may cause fatal warnings if these
semantic restrictions are violated, so one must be careful when generating
The expr is the expression being assigned to this lvalue. We do not in
any way restrict the expression, nor have we found any restrictions discussed
in the Verilog-2005 standard. Even so, it seems there must be some limits.
For instance, what does it mean to assign, say, a minimum/typical/maximum delay
expression? For these sorts of reasons, some transforms may wish to only
permit a subset of all expressions here.
The delay for a continuous assignment is discussed in 6.1.3 (page 71),
and specifies how long it takes for a change in the value of the right-hand
side to be propagated into the lvalue. We represent the delay using a vl-maybe-gatedelay-p; if the delay is nil, it means that no delay
Note (6.1.3) that when delays are provided in the combined declaration and
assignment statement, e.g.,
wire #10 a = 1, b = 2;
that the delay is to be associated with each assignment, and NOT with the
net declaration for a. Net delays are different than assignment delays;
see vl-vardecl for additional discussion.
Warning: Although the parser is careful to handle the delay
correctly, we are generally uninterested in delays and our transforms may not
properly preserve them.
BOZO Presumably the default delay is zero? Haven't seen that yet,
Strengths on continuous assignments are discussed in 6.1.4. We represent
the strength using a vl-maybe-gatestrength-p. If a strength is not
provided, the parser sets this to nil.
Warning: Although the parser is careful to handle the strength
correctly, we are generally uninterested in strengths and our transforms may not
properly preserve them.
- Recognizer for vl-assign structures.
- Fixing function for vl-assign structures.
- Basic constructor macro for vl-assign structures.
- Basic equivalence relation for vl-assign structures.
- Get the strength field from a vl-assign.
- Modifying constructor for vl-assign structures.
- Get the lvalue field from a vl-assign.
- Get the delay field from a vl-assign.
- Get the loc field from a vl-assign.
- Get the expr field from a vl-assign.
- Get the atts field from a vl-assign.