Representation of a clock skew (clocking blocks).
This is a product type introduced by defprod.
- delay — vl-maybe-expr
- Cycle delay amount, e.g., #3, if applicable.
- edge — vl-evatomtype-p
- Edge indicator, or :vl-noedge for edgeless skews.
Clock skews are described in SystemVerilog-2012 Section 14.4. They
indicate when a signal is to be sampled relative to a clocking event.
clocking @(posedge clk);
input #3 foo; // <-- skew is '#3'
input negedge bar; // <-- skew is 'negedge'
input negedge #3 baz; // <-- skew is both 'negedge #3'
Per 14.3 (page 304) input skews are implicitly ``negative'' in that
they say how far before the clock the signal should be sampled; output
skews are ``positive'' and refer to some time after the clock.
Instead of numbers, skews can also be posedge, negedge,
or edge, which indicate that, e.g., that bar above should be
sampled at the negedge of clk. I'm not sure what edge
means or how these combine with delays, but Section 14.4 may be a good
- Fixing function for vl-clkskew structures.
- Basic equivalence relation for vl-clkskew structures.
- Basic constructor macro for vl-clkskew structures.
- Recognizer for vl-clkskew structures.
- Get the edge field from a vl-clkskew.
- Get the delay field from a vl-clkskew.
- Modifying constructor for vl-clkskew structures.