Collect SystemVerilog files from across your design into a single
You can use the vl gather command to collect up Verilog
designs, which might be split across several files in many directories, into a
single file that is otherwise unsimplified.
This kind of consolidation may be useful for a number of reasons, e.g., it
may allow you to quickly do things like grepping through the entire design,
grab a snapshot of the entire design, etc.
Note that if you just want to process designs with VL, there's normally no
reason that you need to use this command. VL's loader can be given
vl-loadconfig options like search-path and include-dirs to
allow it to find modules from many directories.
For usage information, run vl gather --help or see *vl-gather-help*.
- Options for running vl gather.
- (vl-modulelist-original-sources x filemap) maps vl-module-original-source across a list.
- Top-level vl gather command.