Vl-json
Parse a SystemVerilog design and save it as a .json file.
The VL kit provides a json command that you can use to
parse a Verilog/SystemVerilog design and then write it out into a .json
file. These files are complete(?) snapshots of what VL has parsed.
For detailed usage information, run vl json --readme or see *vl-json-readme*.
Subtopics
- Vl-json-opts-p
- Options for running vl json.
- Vl-json-top
- Top-level vl json command.
- *vl-json-readme*
- Detailed usage information for the vl json command.
- Vl-json-main
