Representation of the kind and default for a parameter declaration.
This is a tagged union type, introduced by deftagsum.
Both Verilog-2005 and SystemVerilog-2012 allow parameters to be declared without any explicit type information, e.g., one can write:
parameter size = 5; <-- no explicit type, signedness, or range parameter signed foo = -1; <-- explicitly signed, no explicit range parameter [3:0] bar = 2; <-- explicitly 4 bits, no explicit signedness
The ultimate, post-elaboration type and range of these parameters are described in Verilog-2005 Section 12.2 and in SystemVerilog-2012 sections 6.20.2 and 23.10. These rules are exotic. When no explicit type/range is given, the final type/range is taken from whatever value is ultimately assigned to the parameter. In other cases, i.e., there is only a signedness but no explicit range, or vice versa, then some aspects of the final type/range are determined by the value assigned to the parameter, and other aspects are governed by the parameter declaration itself.
A consequence of these weird rules is that we cannot simply assign some default type to plain parameter declarations. Instead, we need to know that the parameter doesn't have parts of its type specified. To accommodate this, we use vl-implicitvalueparam structures when the type of a parameter is implicitly specified, or vl-explicitvalueparam structures for parameters with explicitly specified types.
All of the above parameters are value parameters. In Verilog-2005, all parameters are value parameters. However, in SystemVerilog-2012, it is also possible to have type parameters (See Section 6.20.3), e.g.,
parameter type bus_t = logic [31:0];
Type parameters are quite different from value parameters. We represent their types as vl-typeparams.