Parse a SystemVerilog design and save it as a .vlzip file,
typically for use with the vl-server.
The VL kit provides a zip command that you can use to
parse a Verilog/SystemVerilog design and then write it out into a .vlzip
file. These files are complete snapshots of what VL has parsed, and also
include the full, raw source code files that have been loaded.
These files are typically used by the vl-server for viewing with the
VL Module Browser. They can alternately be reloaded into ACL2 sessions using
vl-read-zip, which requires very little of VL to be loaded.
For detailed usage information, run vl zip --help or see *vl-zip-help*.
- Options for running vl zip.
- Representation of a .vlzip file's contents. These files can be
used to store pre-parsed Verilog designs.
- Detailed usage information for the vl zip command.
- Top-level vl zip command.