		Search-engine friendly clone of the ACL2 documentation.
Vl-zip
vl-zip-help

Detailed usage information for the vl zip command.
Value:
"
vl zip:  Parse Verilog files and write it out as a .vlzip file.

Example:  vl zip engine.v wrapper.v core.v \\
              --search ./simlibs \\
              --search ./baselibs \\
              --output my-design.vlzip

Usage:    vl zip [OPTIONS] file.v [file2.v ...]

Options:

    -h,--help             Show a brief usage message and exit.
    --readme              Show a more elaborate README and exit.
    -n,--name=NAME        Default is \"design\".  Should be a short name
                          that identifies the project that this zip
                          file is parsing.  This controls how the file
                          will be presented in the \"Choose Model\"
                          screen in the Module Browser.
    -o,--output=FILE      Default is \"design.vlzip\".  Where to write
                          the collected up modules.  Typically this
                          should have a .vlzip extension.
    -s,--search=DIR       Control the search path for finding modules.
                          You can give this switch multiple times, to
                          set up multiple search paths in priority
                          order.
    -I,--incdir=DIR       Control the list of directories for `include
                          files.  You can give this switch multiple
                          times.  By default, we look only in the
                          current directory.
    --searchext=EXT       Control the search extensions for finding
                          modules.  You can give this switch multiple
                          times.  By default we just look for files
                          named \"foo.sv\" and \"foo.v\" in the --search
                          directories.  If you have Verilog files with
                          different extensions, this won't work, so you
                          can add these extensions here.
    -D,--define=VAR       Set up definitions to use before parsing
                          begins.  For instance, \"--define foo\" is
                          similar to \"`define foo\" and \"--define foo=3\"
                          is similar to \"`define foo 3\".  Note: these
                          defines are \"sticky\" and will override
                          subsequent `defines in your Verilog files
                          unless your Verilog explicitly uses `undef.
                          You can give this option multiple times.
    --edition=EDITION     Which edition of the Verilog standard to
                          implement?  Default: \"SystemVerilog\" (IEEE
                          1800-2012).  You can alternately use
                          \"Verilog\" for IEEE 1364-2005, i.e.,
                          Verilog-2005.
    --strict              Disable VL extensions to Verilog.
    -m,--mem=GB           How much memory to try to use.  Default: 4
                          GB.  Raising this may improve performance by
                          avoiding garbage collection.  To avoid
                          swapping, keep this below (physical_memory -
                          2 GB).

"
*vl-zip-help*

vl-zip-help
