Publications by subject

Note: all documents are also available in Postscript; replace the "pdf" extension with "ps" on any link

Processor Architectures

• "Scalable Hardware Memory Disambiguation for High ILP Processors," L. Sethumadhavan, R. Desikan, D.C. Burger, C.R. Moore, and S.W. Keckler
  36th International Symposium on Microarchitecture (MICRO), December, 2003.

• "Universal Mechanisms for Data Parallel Architectures," K. Sankaralingam, S.W. Keckler, W. Mark, and D.C. Burger
  36th International Symposium on Microarchitecture (MICRO), December, 2003.

• "Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture," K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D.C. Burger, S.W. Keckler, and C.R. Moore.
  2003 International Symposium on Computer Architecture (ISCA), June, 2003.

• "Combining Hyperblocks and Exit Prediction to Increase Front-End Bandwidth and Performance,"
  N. Ranganathan, R. Nagarajan, D.C. Burger, and S.W. Keckler.
  UT-Austin Computer Sciences Technical Report TR-02-41, September, 2002.

• "A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems,"
  S.W. Keckler, D.C. Burger, C.R. Moore, R. Nagarajan, K. Sankaralingam, V. Agarwal, M.S. Hrishikesh, N. Ranganathan, and P. Shivakumar.
  2003 International Solid-State Circuits Conference (ISSCC), February, 2003.

• "A Design Space Evaluation of Grid Processor Architectures,"
  R. Nagarajan, K. Sankaralingam, D.C. Burger, and S.W. Keckler.
  34th International Symposium on Microarchitecture (MICRO), December, 2001.

• "Bottlenecks in Multimedia Processing with SIMD-Style Extensions and Architectural Enhancements,"
  D. Talla, L.K. John, and D.C. Burger.
  IEEE Transactions on Computers, 2002.

• "Impact of Technology Scaling on Instruction Execution Throughput,"
  M.S. Hrishikesh, D.C. Burger, and S.W. Keckler.
  UT-Austin Computer Sciences Technical Report TR-00-06, June, 2001.

• "A Technology-Scalable Architecture for Fast Clocks and High ILP,"
  K. Sankaralingam, R. Nagarajan, D.C. Burger, and S.W. Keckler.
  5th Workshop on the Interaction of Compilers and Computer Architecture, at HPCA-7, January, 2001.

• "Guest Editors' Introduction: Billion-Transistor Architectures,"
  D.C. Burger and J.R. Goodman.
  IEEE Computer, 30 (9), September, 1997.

• "DataScalar Architectures,"
  D.C. Burger, S. Kaxiras, and J.R. Goodman.
  24th International Symposium on Computer Architecture (ISCA), June, 1997.

• "Changing Interaction of Compiler and Architecture,"
  S. Adve, D.C. Burger, R. Eigenmann, A. Rawsthorne, M.D. Smith, C. Gebotys, M. Kandemir, D.J. Lilja, A. Choudhary, J. Fang, and P. Yew,
  IEEE Computer, 30 (12), December, 1997.

Technology Modeling

• "Static Energy Reduction Techniques for Microprocessor Caches,"
  H. Hanson, M.S. Hrishikesh, V. Agarwal, S.W. Keckler, and D.C. Burger.
  IEEE Transactions on VLSI, 2002.

• "Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements,"
  P. Shivakumar, M. Kistler, S.W. Keckler, D.C. Burger, and L. Alvisi.
  UT-Austin Computer Sciences Technical Report TR-02-19, April, 2002.

• "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic ,"
  P. Sivakumar, M. Kistler, S.W. Keckler, D.C. Burger, and L. Alvisi.
  International Conference on Dependable Systems and Networks (DSN), June, 2002.

• " The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays,"
  M.S. Hrishikesh, K. Farkas, N.P. Jouppi, D.C. Burger, S.W. Keckler, and P. Sivakumar.
  29th International Symposium on Computer Architecture (ISCA), May, 2002.

• "Assessment of MRAM Technology Characteristics and Architectures,"
  R. Desikan, S.W. Keckler, and D.C. Burger.
  UT-Austin Computer Sciences Technical Report TR-01-36, October, 2001.

• "Static Energy Reduction Techniques for Microprocessor Caches,"
  H. Hanson, V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D.C. Burger.
  International Conference on Computer Design (ICCD), September, 2001.
  Also in UT-Austin Computer Sciences Technical Report TR-01-18, June, 2001.

• "Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures,"
  V. Agarwal, H.S. Murukkathampoondi, S.W. Keckler, and D.C. Burger.
  27th International Symposium on Computer Architecture (ISCA), June, 2000.

• "The Effect of Technology Scaling on Microarchitectural Structures,"
  V. Agarwal, S.W. Keckler, and D.C. Burger.
  UT-Austin Computer Sciences Technical Report TR-00-02, May, 2001.

• "Technology Independent Area and Delay Estimates for Microprocessor Building Blocks,"
  S. Gupta, S.W. Keckler, D.C. Burger.
  UT-Austin Computer Sciences Technical Report TR-00-05. February, 2001.

Memory Systems

• "Guided Region Prefetching: A Cooperative Hardware/Software Approach," Z. Wang, D.C. Burger, S.K. Reinhardt, K.S. McKinley, and C.W. Weems.
  2003 International Symposium on Computer Architecture (ISCA), June, 2003.

• "On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories,"
  R. Desikan, S.W. Keckler, and D.C. Burger.
  UT-Austin Computer Sciences Technical Report TR-02-47, September, 2002.

• "An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches,"
  C.K. Kim, D.C. Burger, and S.W. Keckler.
  International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October, 2002.

• "Filtering Superfluous Prefetches Using Density Vectors,"
  W.F. Lin, S.K. Reinhardt, D.C. Burger, and T.R. Puzak.
  International Conference on Computer Design (ICCD), September, 2001.

• "Designing a Modern Memory Hierarchy with Hardware Prefetching,"
  W.F. Lin, S.K. Reinhardt, and D.C. Burger.
  IEEE Transactions on Computers special issue on memory systems, 50 (11), November, 2001.

• "Reducing DRAM Latencies with a Highly Integrated Memory Hierarchy Design,"
  W.F. Lin, S.K. Reinhardt, and D.C. Burger.
  7th Symposium on High-Performance Computer Architecture (HPCA), pp. 301-312, January, 2001.

• "Hardware Techniques to Improve the Performance of the Processor/Memory Interface,"
  D.C. Burger.
  Ph.D. Dissertation, Computer Sciences Department, University of Wisconsin-Madison, December, 1998.

• " Limited Bandwidth to Affect Processor Design,"
  D.C. Burger, J.R. Goodman, and A. Kägi.
  Invited paper to IEEE Micro, special issue on advanced memory architectures, 17 (6), November/December 1997.

• "Memory Systems,"
  D.C. Burger, J.R. Goodman, and G.S. Sohi.
  The Handbook of Computer Science and Engineering, CRC Press, 1997. Also appears in The Handbook of Electrical Engineering, CRC Press, 1997.

• "System-Level Implications of Processor/Memory Integration,"
  D.C. Burger.
  Workshop on Mixing Logic and DRAM, at ISCA-24, June, 1997.

• "Memory Bandwidth Limitations of Future Microprocessors,"
  D.C. Burger, J.R. Goodman, and A. Kägi.
  23rd International Symposium on Computer Architecture (ISCA), May, 1996.

• "Memory Systems,"
  D.C. Burger.
  ACM Computing Surveys, 28 (1), pp. 63-65, March, 1996.

• "The Declining Effectiveness of Dynamic Caching for General-Purpose Microprocessors,"
  D.C. Burger, J.R. Goodman, and A. Kägi.
  University of Wisconsin-Madison Computer Sciences Technical Report 1261, January, 1995.

Multiprocessor Architectures

• "Exploring the Design Space of Future CMPs,"
  J. Huh, D.C. Burger, and S.W. Keckler.
  International Conference on Parallel Architectures and Compilation Techniques (PACT), September, 2001.

• "Efficient Synchronization: Let Them Eat QOLB,"
  A. Kägi, D.C. Burger, and J.R. Goodman.
  24th International Symposium on Computer Architecture (ISCA), June, 1997.

• "Paging Tradeoffs in Distributed Shared-Memory Multiprocessors,"
  D.C. Burger, R.S. Hyder, B.P. Miller, and D.A. Wood.
  Supercomputing `94, November, 1994.

• "Exploiting Optical Interconnects to Eliminate Serial Bottlenecks,"
  D.C. Burger and J.R. Goodman.
  3rd International Conference on Massively Parallel Processing Using Optical Interconnects (MPPOI), October, 1996.

Simulation

• "Sim-alpha: a Validated, Execution-Driven Alpha 21264 Simulator,"
  R. Desikan, D.C. Burger, S.W. Keckler, and T.M. Austin.
  UT-Austin Computer Sciences Technical Report TR-01-23, October, 2001.

• "Measuring Experimental Error in Microprocessor Simulation,"
  R. Desikan, D.C. Burger, and S.W. Keckler.
  28th International Symposium on Computer Architecture (ISCA), July, 2001.

• "SimpleScalar Simulation of the PowerPC Instruction Set Architecture,"
  K. Sankaralingam, R. Nagarajan, S.W. Keckler, and D.C. Burger.
  UT-Austin Computer Sciences Technical Report TR-00-04, February, 2001.

• "Memory Hierarchy Extensions to the SimpleScalar Tool Set,"
  D.C. Burger, A. Kägi, M.S. Hrishikesh.
  UT-Austin Computer Sciences Technical Report TR-99-25, September, 1999.

• The SimpleScalar Tool Set, Version 2.0,"
  D.C. Burger and T. M. Austin.
  Computer Architecture News, 25 (3), pp. 13-25, June, 1997. Extended version appears as UW Computer Sciences Technical Report 1342, June, 1997.

• "Evaluating Future Microprocessors-the SimpleScalar Tool Set,"
  D.C. Burger, T. M. Austin, and S. Bennett.
  UW Computer Sciences Technical Report 1308, July, 1996.

Application Evaluation

• "A Characterization of Speech Recognition on Modern Computer Systems,"
  K. Agaram, S.W. Keckler, D.C. Burger.
  4th IEEE Workshop on Workload Characterization, at MICRO-34, December, 2001.

• "Characterizing the SPHINX Speech Recognition System,"
  K. Agaram, S.W. Keckler, D.C. Burger.
  UT-Austin Computer Sciences Technical Report TR-00-33. January, 2001.

• " Parallelizing Appbt for Shared-Memory Multiprocessors,"
  D.C. Burger and S. Mehta.
  University of Wisconsin-Madison Computer Sciences Technical Report 1286, September, 1995.

Miscellanea

• "A Neuroevolution Method for Dynamic Resource Allocation on a Chip Multiprocessor,"
  F.J. Gomez, D.C. Burger, and R. Miikkulainen.
  International Joint Conference on Neural Networks (IJCNN), July, 2001.

• Software to accompany Exploration Geophysics of the Shallow Subsurface,
  D.C. Burger and H.R. Burger.
  Prentice-Hall, Inc., 1992.

• "Exploration Geophysics-An Interactive Approach,"
  H.R. Burger and D.C. Burger.
  Geological Society of America, Abstracts with programs, 21, p. A369, 1989.